The University of Iowa's DEC PDP-8Restoration Log
Part of
the UI-8 pages
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The University of Iowa's DEC PDP-8Restoration Log
Part of
the UI-8 pages
|
This is a chronological log of the progress restoring the University of Iowa's PDP-8 computer. Entries are added at the end as work progresses. Click on any thumbnail image to see full-sized image.
Bug 64: After a long hiatus forced on us by the COVID-19 epidemic, the retrocomputer lab was reopened during the fall of 2022. We went over many of the same ssues covered in previous years, verifying that memory didn't seem to be working and renewing our suspicion that there might be a problem with the memory strobe signal.
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| Three probes |
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In the photo
Doug Jones built one probe while Elle Goodrich and Samuel Nicklaus built the
other, learning to solder and doing some logic debugging in the process,
locating inadvertent cold solder joints, forgotten connections and solder
bridges.
Bug 64: The instructions for setting the memory read and inhibit currents ask that this be measured relative to the BT2A timing signal, so we used a scope to look for the BT2A timing signal on pin MD30U, which is the output of a W640 pulse amplifier. See drawing BS-D-8M-0-16 In/Out buffers on pages 10-53 and 10-54 of the Maintenance Manual (F-87 2-66). We got a flat line on the output of this pulse amplifier, so we traced back to its input, T2A on MF36H. This traces back to PF1H.
Looking at drawing
BS-D-8P-0-9 Timing, Keys, Switches, and Run Control
on pages 10-41 and 10-42 of the
Maintenance Manual,
we traced T2A to PB36M, shown on the schematic as the
output of an R603 pulse amplifier. In fact, it is an S603, a board with
different resistor values but the same layout.
Again, it was a flat line. The input, on PB36K, however, was good.
From this, we concluded that the S603 was bad.
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| R603 board layout |
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Going over the board with a voltmeter, checking the diodes, we found that D13
was shorted, conducting equally well forward and reverse. Replacing this
diode gave us a clock signal where we expected it.
Bug 64: We used a scope to check the memory timing waveforms shown in Figure 4-5 on page 4-11 of the Maintenance Manual (F-87 2-66). The T1 and T2B waveworms looked like reasonably good 100ns pulses, but the MEMORY START waveform, which should also have been a 100ns pulse, was a distorted square wave.
This led us back to drawing BS-D-8P-0-9 Timing, Keys, Switches, and Run Control on pages 10-41 and 10-42 of the Maintenance Manual. There, the master clock drives a flipflop called TG that produces a square wave from which T1, T1E, T2A, T2B, and T2E are derived using R602 and R603 pulse amplifiers. MEMORY START is derived, through an additional R603 pulse amplifier, from T2B.
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| Clock and MEM START waveforms |
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Note, we got a PicoScope 2206B 50Mhz 2-channel USB oscilloscope. The image
here is a composite of 4 screen-shots of this scope, all with TG as input to
channel 1, used to trigger the scope while channel 2 is used for the
other signal being measured.
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| Table plans |
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Bug 64: Our work on Oct 28 led us to drawing BS-D-8M-0-15 Sense Amps, Inhibit Drivers and Memory Control, on pages 10-51 and 10-52 of the Maintenance Manual (F-87 2-66). This showed us that there is no wire in the CPU carrying the MEM START pulse because that pulse is tied directly to the 1 output of the READ flipflop, a B204 board in slot MD16.
According to the datasheet for the B204 in the Digital Logic Handbook (1967), "each flip-flop may be individually set by grounding the 0 output and may be cleared by grounding the 1 output." As a result, wiring MEM START to an output of the flipflop means that the leading edge of the MEM START pulse will set the flopflop which will then hold MEM START high until the flipflop is reset.
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| Clock, MEM START and READ |
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With the B204 board back in place, the waveform on the MEM START line becomes the READ signal. To verify that the B204 flip-flop in slot MD16J was behaving correctly, we looked at the inverse READ signal on pin MD16J. Looking at the traces to the left, it is easy to see that the middle READ trace is effectively the maximum of MEM START and the inverse of READ.
The bottommost READ trace here is the output of the bus
driver in slot MC16. The output of this bus driver is also
READ and
comparison of the two READ traces shows that the bus driver
cleans up the signal at the cost of a slight delay. Note that the bus driver
used on our machine is not an R650 as shown in drawing BS-D-8M-0-15.
Instead, it is a
B684 dual bus driver. The B684 bus driver has its output on
pin D, while the R650 has its output on pin J.
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| Figure 4-5, as measured |
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The MEM STROBE pulse is specified as a 40ns pulse in Figure 4-5, and measures almost exactly that long. As measured, MEM START and MEM DONE look identical, although Figure 4-5 tells us that MEM START should be a 100ns pulse while MEM DONE should be 70ns. Both are close fits to the description of a 100ns pulse in Figure 10-3 on page 4-11 of the Maintenance Manual.
Conclusion: The memory timing is good.
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| Inhibit and R/W currents |
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The BT2A pulse is about 410ns long. According to drawing BS-D-8M-0-16 In/Out Buffers on pages 10-53 and 10-54 of Maintenance Manual (F-87 2-66), this is derived from BT2, which should be a short pulse, 70ns to 100ns long. BT2A is the output of the W640 pulse output converter in slot MD30. Accoring to the datasheet for the W640, it converts a 70ns or longer input pulse to a 400ns output pulse. The datasheet also warns, concerning the output "pulse transformer backswing at the end of each pulse. When the load is light, this transformer recovery spike approaches the amplitude of the pulse itself." This exactly matches what we see in the scope trace.
Conclusion: Aside from questions of current amplitude, which is off by a small
amount, the memory INHIBIT, READ and WRITE pulses all look good.
Bug 64: We followed the instructions in the PDP-8 Memory Tuning Procedure (also available here) for setting the inhibit current to 310mA (it had been 330mA) (page 7), the R/W pulse amplitude to 330mA (it had been 320mA) (page 8), the second-stage clamp to 7.2V (it had been lower) (page 9), and the slice voltage to 7.2V (it had been higher) (page 12).
This did not fix the memory, so we took the time to investigate how data from the sense amplifiers reaches the memory buffer register MB. What we found is that the 0→MB signal directly clears the MB register at the start of each read cycle, and then each sense amplifier sends a set pulse (if needed) to the corresponding bit of MB in response to MEMORY STROBE. The data paths in question proceed from drawing BS-D-8M-0-15 Sense Amps, Inhibit Drivers and Memory Control, on pages 10-51 and 10-52 of the Maintenance Manual (F-87 2-66) to drawing BS-D-8P-0-5 MB Register and Control on pages 10-35 and 10-36 of the manual.
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| Memory Strobe and 0→MB |
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For completeness, we also checked the switching threshold for the strobe input to the sense amplifiers. Looking at drawing RS-B-G007 Sense Amplifier, on page 10-9 of the Maintenance Manual, we found that this threshold should be about -0.8V, assuming 0.6V for a forward biased junction plus about 0.2V for a saturated transistor.
Our conclusion from this effort is that the data path to the MB register
should work. Therefore, our problem is in the core memory or in the
sense amplifiers.
Following the instructions on page 9 of the PDP-8 Memory Tuning Procedure (also available here), we adjusted the second stage clamp voltage output from the G008 Master Slice Control in slot MB31. After doing this, we checked the static balance as instructed on the same page, and found things were a bit out of whack. We got the following voltages, measuring from the two differential outputs to ground:
| 25 | 26 | 27 | 28 | 29 | 30 | ||
|---|---|---|---|---|---|---|---|
| MA | E | 8.0 | 7.8 | 8.2 | 8.0 | 7.9 | 7.9 |
| F | 7.8 | 8.0 | 7.6 | 7.7 | 7.9 | 8.0 | |
| MB | E | 8.1 | 8.0 | 8.1 | 7.9 | 7.9 | 8.0 |
| F | 7.8 | 8.0 | 8.0 | 8.0 | 8.0 | 7.9 | |
The next step was to measure the voltage between pins E and F of each sense amplifier on the most sensitive scale of the voltmeter while using the potentiometer on each sense amplifier to try to get the difference to zero. Our result was:
| 25 | 26 | 27 | 28 | 29 | 30 | |
|---|---|---|---|---|---|---|
| MA | 0.0 | 0.0 | 0.0 | -.1 | 0.0 | 0.0 |
| MB | -.1 | .07 | -.22 | 0.0 | 0.0 | 0.0 |
You are supposed to be able to get the voltages within 25 millivolts of each other and differences of 75 millivolts are considered problematic. We were unable to get the sense amplifier in MB27 closer than 70 millivolts. This suggests that this sense amplifier may be marginal, creating Bug 66.
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| Sense amp. and slicer outputs |
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It is clear from the above measurements that the sense amplifier we checked
was well balanced, and that the slicer is working. This leaves us at a
loss as to why we get no data.
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| Sense and slicer when reading 0 |
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| Sense and slicer when reading 1 |
The first obvious observation from these plots is that writing 0 and writing 1 to memory are different. The big difference between these is that one involves an inhibit pulse and one does not. Apparently, the 0 case involves an inhibit pulse, and the 1 case does not. Furthermore, it appears that all of the signals we observed on the sense line are noise from this inhibit pulse.
The second observation is that the strobe pulse arrives when there is no
activity in memory, as if there was no read pulse at all! The actual switching
of the read pulses is complex, involving an array of 8 G209 Memory Selector
boards, which drive 8 G603 Memory Selector Matrix boards which drive
the 64 X and 64 Y select lines of the core memory.
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| MA11 and its inverse? |
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The scope trace here shows expected data on MA11(1), but MA11(0) is corrupted
by extreme noise, with an amplitude close to the signal amplitude. Something
is seriously wrong here, creating
Bug 67.
MA11 with no G209 boards. |
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MA11 with just G209 in MD13. |
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MA11 with G209s in MD13-15. |
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MA11 with no G209 boards. |
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Using an ohm-meter on the 10Ω scale to check the board removed from backplane slot MD12, we found that D1, D2, D3, D7, D9, D33, D35, D49, D50 and D51 all showed non-infinite reverse resistance. In contrast, on working boards, these all show infinite reverse resistance. D2 and D17 were completely shorted. We replaced all of them.
All of the bad diodes were in the bottom (or B-side) column of diodes on the board (the left side as shown to the right); these are all part of and gates used for address decoding on the B side of the G209. This leads us to suspect something systematic has damaged them.
Note that drawing
BS-D-8M-0-12 X Axis Selection
on pages 10-47 and 10-48 of the maintenance manual
shows that the A side of the G209
(plugged into a slot in row C of the backplane)
is used to switch the positive side of the read/write pulse, while
the B side (in row D) switches the negative side. Did something odd happen on
the negative side? We will have to check the diodes on all the G209 boards
to assess this.
