Arjun Viswanathan

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I am a PhD student at the University of Iowa, working with Prof. Cesare Tinelli. I completed my Master's in Computer Science at the University of Iowa, in Spring 2017. My research interests currently are in SMT (satisfiability modulo theories) solvers, proof assistants, and - in general - logic in computer science. I contribute to CVC4, the SMT-solver co-developed by Professor Tinelli's team at the University of Iowa, and Kind2, the model checker.

My long-term goals, besides successfully completing my PhD, are to equip myself to efficiently teach fundamental computer science courses.

I am from South India, and graduated from MVJ College of Engineering at Bangalore, in 2015.



Department of Computer Science
1420 Seamans Center
University of Iowa
Iowa City, IA 52242-1419


arjun-viswanathan @



Fall 2015 - Teaching Assistant, Introduction to Computer Science
Fall 2016 - Teaching Assistant, Algorithms
Spring 2017 -
Teaching Assistant, Programming Language Concepts
Fall 2018 - Teaching Assistant, Formal Methods in Software Engineering


Summer 2016 - SAT/SMT/AR Summer School, Lisbon, Portugal
Fall 2016 - Midwest Verification Day 2016, Ames, Iowa, USA
Summer 2017 - Verification Mentoring Workshop, Heidelberg, Germany
Summer 2017 - Computer-Aided Verification 2017, Heidelberg, Germany
Fall 2017 - Midwest Verification Day 2017, Manhattan, Kansas, USA
Summer 2018 - DeepSpec Summer School 2018, Princeton, New Jersey, USA
Fall 2018 - Midwest Verification Day 2018, Iowa City, Iowa, USA


Datatypes with Shared Selectors
Andrew Reynolds, Arjun Viswanathan, Haniel Barbosa, Cesare Tinelli, and Clark Barrett. International Joint Conference on Automated Reasoning (IJCAR) 2018.

Comparison of Proof Producing Systems in SMT Solvers
Arjun Viswanathan. Report presented as part of Qualifying Exam on 09/18/2018.

Verifying Bit-vector Invertibility Conditions in Coq (Extended Abstract)
Burak Ekici, Arjun Viswanathan, Yonin Zohar, Clark Barrett, Cesare Tinelli. Proof eXchange for Theorem Proving (PxTP) 2019