I am a PhD student at the University of Iowa, working with Prof. Cesare
Tinelli. I completed my Master's in Computer Science at
the University of Iowa, in Spring 2017. My research interests
currently are in SMT (satisfiability modulo theories) solvers,
proof assistants, and - in general - logic in computer science.
I contribute to CVC4,
the SMT-solver co-developed by Professor Tinelli's team at the
University of Iowa, and Kind2, the model
My long-term goals, besides successfully completing my PhD, are
to equip myself to efficiently teach fundamental computer
I am from South India, and graduated from MVJ College of
Engineering at Bangalore, in 2015.
Department of Computer Science
1420 Seamans Center
University of Iowa
Iowa City, IA 52242-1419
arjun-viswanathan @ uiowa.edu
Fall 2015 - Teaching Assistant, Introduction to Computer
Fall 2016 - Teaching Assistant, Algorithms
Spring 2017 - Teaching Assistant, Programming Language Concepts
Fall 2018 - Teaching Assistant, Formal Methods in Software Engineering
with Shared Selectors
Andrew Reynolds, Arjun Viswanathan, Haniel Barbosa, Cesare Tinelli, and Clark Barrett. International Joint Conference on Automated Reasoning (IJCAR) 2018.
Comparison of Proof Producing Systems in SMT Solvers
Arjun Viswanathan. Report presented as part of Qualifying Exam on 09/18/2018.
Verifying Bit-vector Invertibility Conditions in Coq
Burak Ekici, Arjun Viswanathan, Yonin Zohar, Clark Barrett, Cesare Tinelli. Proof eXchange for Theorem Proving (PxTP) 2019