Some Core Memory

An HP9100B core memory module

Memory for a programmable calculator

Part of the Core Memory pages
by Douglas W. Jones
THE UNIVERSITY OF IOWA Department of Computer Science



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This memory module from a programmable desk calculator consists of 2 boards 10.5 inches (287 mm) wide by 4.75 inches (121 mm) high with a diagonal slice out of the top rear to accomodate the sloping rear of the calculator's case. The boards are 0.056 inches (1.42 mm) thick and spaced on 5/8 inch (15.9 mm) centers, bridged at the top with a connector block. The assembly plugs into the horizontal mother board on the bottom of the calculator where the long dimension of the boards runs from front to back. All of the boards have the [(hp)] logo and MADE IN USA etched into them, and all are completely gold plated, as was typical of HP electronics in the 1960s and into the 1970s.

Various sources document this calculator as having 32 registers, each able to hold either 12 decimal digits (2 exponent, 10 mantissa) or 12 6-bit instructions, plus a 3-level stack (the X, Y and Z registers). This is 35 registers of 72 bits each, or a total of 2520 bits. This is considerably less than the 4416 bits reported by some sources, but this is a deeply microprogrammed machine with primitive operations in its user-level instruction set that include trig functions. Presumably, much or all of the rest of the core memory is used for variables needed by the microcode to implement the calculator's user level instruction set.

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The left board (marked 09100-66553 REV C) contains the addressing logic for the memory. This is all discrete transistor-diode logic. There are 99 transistors, the small round metal cans in the photo, and 52 capacitors, the orange blobs in the photo. If we assume that the capacitors are in series with memory addressing lines, we can conclude that 32 addressing lines leave the board by the top connector and 20 leave by the bottom connector.

The use of mother board wiring for communication between the two boards of the module suggests that the mother board is not organized with any kind of bus structure. Rather, it appears that the different slots are each dedicated to a specific function, and that the mother board wiring is random, supporting those functions. In fact, most of the area of the mother board is devoted to huge numbers of diodes that make up the ROM holding the low-level microcode.

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The right board (marked 09100-66554 REV B) holds the core plane itself plus 6 sense-inhibit drivers, each of which consists of a cluster of 7 small transistors and one big transistor. Looking at the connections to the core plane, it appears that the sense amplifier and inhibit drivers are electrically separate. At the rear side of the board, there are 4 more transistors, presumably involved with global function of the board.

The central feature of this board is the core plane itself. The speculation that the top connector is used for communication with the addressing logic is confirmed by the fact that the printed circuit traces from this connection all lead directly to the core plane, along with 20 of the traces from the front mother board connector.

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The core plane is mounted on the underside of a daughter board 2.25 inches (57 mm) wide by 4.125 inches (105 mm) high directly under the connector block that bridges the two boards, and further protected by a clear plastic cover that clips to the daughter board. The daughter board is mounted 9/32 inches (7.14 mm) above the surface of the sense/inhibit board, supported by gold-plated pins on 0.1 inch (2.54 mm) centers, arranged as 4 groups of 8 around the top end, 2 groups of 10 on the sides, and a row of 21 pins at the bottom.

Becaise the pins joining the daughter board to the sense/inhibit board are soldered at both ends, removing the daughter board for direct examination of the core plane would pose a great risk of permanent damage. Therefore, the best we can do is peer into the congested space between the boards and look at the shadows visible through the boards. A bit of image enhancement was used to bring out the details of the circuit traces on the hidden side of the daughter board.

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Looking at the shadows, it is appears that the core is wired with 20 select lines on the X axis, connected at the bottom of the photo to the right. There are two groups of 10, and each line appears to run up the length of the core, turn around and the return to a common return (the T-shaped shadow that divides the two groups of 10.

On the Y axis, there appear to be 16 connections at the top left and 16 connections at the top right. These are not aligned with each other, so there are not 16 lines that go across the core plane there. Rather, it would seem that the 16 connections from each side cross the top patch of core and then weave down across a middle patch before exiting at the bottom where there is a row of 16 connections visible in shadow on each side, connected to a common return trace.

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From this, we can infer that the core plane contains 6 patches, corresponding to the 6 bits per digit or instruction, each intersected by 20 X-select lines and 32 Y-select lines giving a total of 640 6-bit digits or 3840 bits. The figure to the right shows the arrangement inferred here, with the routing of the topmost, bottommost, leftmost and rightmost wires in each patch shown. This is exactly the same number given in the HP's 1970 catalog (see below), lending some confidence to the reverse engineering effort above. This disagrees with several secondary sources that have simply doubled the number from published figures for the HP9100A.

Close examination of the group of 10 connections on the middle of each side of the core plane shows that each group is arranged as 3 groups of 3, with traces from each group diverging to one of the 6 sense-amplifier inhibit-driver clusters. the 10th connection on each side used for a common pin connected to many wires. If there are 3 sense-inhibit connections to each of 6 patches of core, this implies that 4 wires pass through each core, X, Y, sense and inhibit. It is likely that each end of the sense line is connected to two pre-amplifier transistors in each cluster, while the inhibit line goes from a power driver transistor to a common return point.

In any case, the actual core memory plane appears to occupy an area 1.625 inches (41.3 mm) wide by 3.25 inches (82.6 mm) high.

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The connector block bridging the two boards consists of a pair of Cinch card-edge connectors, each with 36 contacts, 18 on each side of the board, on 5/32 inch (3.97 mm) centers. The circuit board linking the two connectors on each block is numbered 0911-66568 REV A.


There is considerable documentation available for the HP9100A. HP published detailed descriptions of the machine in the Hewlett-Packard Journal, Sept. 1968 and many of the available peripherals are documented in Hewlett-Packard Journal, Oct. 1970. Unfortunately, neither of these publications covers the detailed organization of the HP9100B core memory. Pages 82-85 of Hewlett-Packard's 1970 Electronics for Measurement, Analysis, Computation catalog gives the price of HP9100B as $4900 and states that the machine has 3840 bits of core memory. Page 61 of Service Manual, Hewlett-Packard Calculators Models: 9100A, 9100B lists the Core Driver Ass'y/ Core Sense Amplifier as a single field replacable part (part number 9100-69595), to be returned to HP for repair if replaced.

Most end-user discussion of the speed of the 9100 focuses on the time per floating point add, typically 2 milliseconds. Because the machine operates on floating point numbers in a digit-serial manner, this involved lots of memory references. Digging deeper, it appears that the core memory had a cycle time of 1.6 microseconds. This is given in fine print in the Specifications on page 9 of the Hewlett-Packard Journal, Sept. 1968.


The calculator was purchased new from HP by Dr. Charles Wunder, and came to this collection in operating condition when he retired from his position in the Physiology department. Wunder and James Van Allen were the two faculty members at Iowa who made the most extensive use of calculators in the HP9100 family. Wunder's calculator was equipped with a digitizing tablet, plotter and printer.

Searching for evidence of the actual data of manufacture turns up the following markings:

None of these appear to be dates, unless the leading digit on the quality assurance stamps is the last digit of the year, indicating that the board was made in 1969. If so, the 132 and 138 might indicate the day in the year, in which case, 9-132 would be Monday May 12, 1969, and 9-138 would be Sunday, May 18. (According to Rick Bensene, HP's 9100 production line was running 7 days a week, so these dates are plausible.)

Some of the electrolytic capacitors on the core sense-inhibit board by the side of the daughter board are marked:


It is likely that the 7013 on these capacitors is a manufacturing date code, in which case, these capacitors were made in the 13th week of 1970 (in April) and the board must have been assembled later, probably later that year. In this case, the QA date stamps on the board are the quality control dates for the board etching and plating, not the final assembly date, and HP would have made a batch of board over a year in advance of their final assembly.


The feed rollers for the printer and the magnetic card reader used for program storage have long-since turned to goo, but the calculator itself was fully functional when last powered up.