In the late 1960's, IBM introduced the 360 model 91; this was the first commercial offering of a pipelined computer, if one ignores the fact that certain aspects of the CDC 6600 computer could be viewed, in retrospect, as pipelined.
The IBM System 360 family of computers had a common architecture, that is, a common instruction set, as seen by the users, with a wide variety of implementations. Vertical microcode (with large numbers of short microinstructions per instruction) and horizontal microcode (with a small number of long microinstgructions per instruction) were both used for some members of this family.
It is worth noting that the System 360 family is alive and well today. The number was coined by marketing to mean a 3rd generation machine for the 1960's, so, of course, when the 1960's ended, marketing considerations demanded a change of numbering, so the 370 family was born. In the 1980's, a new and somewhat scrambled numbering system obscured what was going on, but in the 1990's, the 390 family carried on the tradition. Today's representatives of this family remain object-code compatable with the original for user programs, despite immense changes in the implementation technology, the I/O architecture, and the operating system environment.
The IBM System 360 family is characterized by a 32-bit word, and 16
general purpose registers.
The basic instruction format of the IBM System 360 was and is:
8 4 4 4 12
| | |
OP R X B DISP
L (load) GPR[R] = M[ GPR[X] + GPR[B] + DISP ]
LA (load address) GPR[R] = GPR[X] + GPR[B] + DISP
ST (store) M[ GPR[X] + GPR[B] + DISP ] = GPR[R]
A (add) GPR[R] = M[ GPR[X] + GPR[B] + DISP ] + GPR[R]
BAL(branch and link) PC = GPR[X] + GPR[B] + DISP; GPR[R] = PC
8 4 4
OP R X
BALR (branch and link) PC = GPR[X]; GPR[R] = PC
There are hunddreds of texts on programming this family of machines
(The assembly language was BAL, the Basic Assembly Language, so
many texts are catalogued under this and not under IBM 360).
The purpose of the above list of instructions is not to provide
anything like an exhaustive list! Rather, it is to illustrate
the kinds of operations the the underlying hardware must execute
for each instruction execution cycle.
During any cycle, the machine may fetch a 16-bit halfword instruction or a 32-bit full-word instruction. In executing this instruction, it may perform any of the following operations:
The memory reference for operands is certain to take as long as an instruction fetch, and it is quite possible to imagine a system where the time to perform arithmetic operations is comparable to the time taken to access memory. This leads to the suggestion that this architecture could be pipelined with the following pipeline stages:
Given the above breakdown of an instruction set into pipeline stages, the first question that must be resolved is: What goes in the interstage registers?
_______ _______ |_______| |_______| IR NEXT PC
_______ _______ _______ |___////| |_______| |_______| IR R EA
Certain fields of the instruction register are no-longer needed at this point. The displacement and base register B have been used, and for all of the example instructions, there is no further need for the index register X.
_______ _______ _______ |___////| |_______| |_______| IR R OP