22C:122/55:132, Lecture Notes and Schedule, Spring 2001

Lectures are at 9:30 Monday, Wednesday and Friday, Room 103, North Hall
with a video link to the Grant Wood room, Bldg 133, Rockwell Collins.

This schedule is preliminary expect revisions!

Wed Jan 17 -- Introduction

Fri Jan 19 -- A breakneck review of digital logic

Mon Jan 22 -- A breakneck review of finite state automata

Wed Jan 24 -- A breakneck review of register transfer components

Fri Jan 26 -- Reduction of programs to register transfer systems

Mon Jan 29 [Last free drop/add] -- A hardware description language

Wed Jan 31 -- The Ultimate RISC at the ISP level

Fri Feb 2 -- The Ultimate RISC at the Register Transfer level

Mon Feb 5 [Last add] -- More Register Transfer design

Wed Feb 7 -- Review of bus-level design

Fri Feb 9 -- Bus Level Components for the Ultimate RISC

Mon Feb 12 -- Information Theory and Instruction Coding

Wed Feb 14 -- Stack machines: The Minimal CISC at the ISP and RT levels

Fri Feb 16 -- Optimal Instruction Coding for Stack Machines

Mon Feb 19 -- Fast addition

Wed Feb 21 -- Fast multiplication

Fri Feb 23 -- Class Cancelled! (Junior College Articulation Conference)

Mon Feb 26 -- Fast Multiplication without hardware support!

Wed Feb 28 -- BCD Arithmetic

Fri Mar 2 -- Coprocessors (simple case of functional units)

Mon Mar 5 -- review and wrap-up simple coprocessors

Wed Mar 7 [Midterm] -- Exam

Fri Mar 9 -- Pipelined functional units, vector processors

Mar 10-18 [Spring Break]

Mon Mar 19 -- VLIW processors

Wed Mar 21 -- VLIW processors with pipelines

Fri Mar 23 -- Pipeline diagrams

Mon Mar 26 -- A Classic Pipelined CPU

Wed Mar 28 -- Implementing a pipelined CPU

Fri Mar 30 -- Interlock conditions

Mon Apr 2 [Last undergrad drop] -- Interlock logic, branches and skips

Wed Apr 4 -- Forwarding, out-of-order execution

Fri Apr 6 -- Variable length instructions

Mon Apr 9 [Passover, day 2] -- Superscalar pipelines

Wed Apr 11 -- Condition codes and conditional branches

Fri Apr 13 [Good Friday] -- Calls and interrupts

Mon Apr 16 [preregistration] -- Interrupts in pipelined systems, Imprecise Traps.

Wed Apr 18 -- Bus Arbitration, Crossbar Switches

Fri Apr 20 -- Use of Cache Memory

Mon Apr 23 -- Implementing Associative and Cache Memory

Wed Apr 25 -- Snooping caches

Fri Apr 27 -- Banyan trees, cached and crossbar based

Mon Apr 30 -- Branch prediction (more associative memory)

Wed May 2 -- Alignment networks and Memory management units

Fri May 4 -- Loose ends!

Final Exam

Fri May 11, 7:30 AM