No computer needs a bus. All digital systems that use busses can can be built, in theory, using multiplexors and demultiplexors to serve the same function. Early computers from the late 1940's generally were not based on busses!
Bus-oriented design has some important advantages:
Sidenote The term bus in electronics comes from the term bus-bar in power-plant design; this term may date back to Edison. In a classical power plant, with many dynamos powered by piston engines, a pair of copper bars was used to combine the outputs of the dynamos and transfer the output to the various power transmission lines leading from the plant. These bars, taken together, were the bus for the powerplant. The topology of the entire system was quite similar to the topology of a computer system with its own bus, except that the subsystems were dynamos and external transmission lines, and there were only two conductors in these early busses.
Physically, a typical bus consists of many wires. Some are ground or return wires, required to complete the electrical circuits of the underlying electronics, and some are signal lines.
Because the lines in a bus are typically relatively long, they must be driven using more power than the short lines carrying logic signals within a subsystem. Furthermore, long lines are more likely to act as antennas than short ones, picking up interference from the outside world. Because of this, we generally use bus receivers, special circuits with a better noise rejection characteristic than the common logic circuits. Aside from this distinction, the actual encoding of logical values on bus lines is typically similar to that used elsewhere in the digital system.
When a bus is long enough that the transmission time on the bus is significant compared to the speed of the logic used in the system, echoes from the ends of the bus must be controlled. This is done using bus terminators. Typically, these are resistor networks at the ends of the bus, matched to the characteristic impedance of the bus lines, and connected to either ground, the logic supply voltage, or a carefully selected neutral intermediate voltage.
Bus lines can be divided into two categories:
The bus drivers for single-source lines are typically merely high-power versions of normal logic outputs.
The bus drivers for multiple-source lines must be special, able to either deliver a logic signal to the line or to disconnect, allowing some other source to deliver a signal.
There are two kinds of drivers appropriate for a multiple-source bus line. Both are common in digital systems:
Open-collector or open-drain busses are limited in speed because the passive pull-up of the terminator can't drive a one onto the line as quickly as an active bus driver could. They are simpler, however, and are common on short low-performance busses.
Tri-state drivers are fast. A typical tri-state driver is described as follows:
a b | c c | ------|------ | 0 0 | open | 0 1 | open a ---/_\ 1 0 | 0 | 1 1 | 1 b |
Bus-based systems may be divided into two groups:
Typically, the master is the only device able to drive the single-source bus lines, while the slaves all use drivers compatable with multiple-source lines. For example, the master may drive the address lines while each slave listens for its address and reads or writes data only when the address lines select it.
Multimaster busses require some way to resolve bus contention when multiple masters each wish to use the bus at the same time. Bus contention logic is a complicated problem, and in fact, there is no solution to the problem of resolving the contention problem in a fixed finite time without the use of a centralized arbitrator.
Most multimaster busses are not completely asynchronous, but instead, have a central clock that delivers a single synchronized stream of clock pulses to all devices on the bus. The master clock is sometimes packaged with a small amount of contention resolution logic and the bus terminators in a bus controller subsystem.
A typical single master bus might be designed as follows:
---------- | |----------------------- Data (tristate) | |----------------------- Lines | | | |-\--------------------- Address (single source) | BUS |-/--------------------- Lines | MASTER | | |->--------------------- Direction (read or write) | | (single source) | |->--------------------- Strobe or clock | | ----------We can describe a the bus cycless on this system as follows:
read cycle write cycle | ________ ________ data |-------________----------________---- | | __________ __________ address |-----__________--------__________---- | | _________________ direction |____________________ | | ___ ___ strobe |_________ _______________ _______ | -|-------------------------------------- |In the above, the following notation is used:
| ________________ |------------------________________--- | invalid or no valid (each line | defined value in this group is | either 0 or 1)During a read cycle, we speak of the delay between address valid and data valid. This is the read-time of an unclocked device. The receiver of the data being read only looks at the data during the strobe pulse. During a write cycle, we talk about the delay between data valid and the strobe pulse. This is the setup-time of a clocked write device. The total delay from address valid to the significant edge of the clock pulse, typically the read-time plus the setup time, must be shorter than the time from address valid to the significant edge of the clock pulse.