16. The Sparrowhawk Subset

Contents

16.1. The Subset
16.2. Code Conversion

16.1. The Subset

Strictly speaking, many of the instructions in the Hawk instruction set are unnecessary. Omitting some of these instructions can greatly simplify the hardware.

The Sparrowhawk subset of the Hawk instruction set omits all 32-bit instruciton formats. Specifically, there are no long immediate instructions no long memory reference instructions and no coprocessor instructions.

Use of the opcodes assigned to these instructions on a Sparrowhawk processor results in an instruction trap. Operating systems on the Sparrowhawk may virtualize the missing instructions using an appropriate trap service routine, allowing Sparrowhawk processors to run aribtrary code written for the Hawk.

16.2. Code Conversion

Most Hawk code can be converted to the Sparrowhawk subset by making local substitutions that replace single Hawk instrucitons with sequences of Sparrowhawk instructions that do the same thing. In some cases, this requires use of at most one temporary register; in these cases, if no register is available, additional changes to the original code are required. In addition, these changes can expand the original code to the point that some PC-relative addresses are out of bounds, requiring even more changes.

For LIL instructions, replace:

        LIL     R5,CONST

With an LIS followed by an appropriate sequence of ORIS instructions. In the general case, this gives:

        LIS     R5,(CONST>>16)
        ORIS    R5,(CONST>> 8)&#FF
        ORIS    R5,(CONST    )&#FF

If the constant can be represented in 16 bits, this code suffices:

        LIS     R5,(CONST>>8)
        ORIS    R5,(CONST   )&#FF

For memory reference instructions, a register must be used for effective address computation. Here, we will use R1 as a temporary because this register is commonly used for subroutine linkage and therefore routinely unsafe to use for long-term operand storage.

Taking STORE as the prototypical memory reference instruction, we can replace:

        STORE   R5,R2,DISP

With an appropriate load immediate followed by an add prior to storing the operand. In the general case, this gives:

        LIS     R1,(DISP>>8)
        ORIS    R1,(DISP   )&#FF
        PLUS    R1,R2           ; compute the effective address
        STORES  R5,R1           ; load the operand

Note the use of the PLUS instruction to compute the effective address. This was needed here because STORE does not change the condition codes.

The above substitution can be made for all memory reference instructions, but many optimizations are possible. When the displacement is short, the ORIS instruction may be omitted. In the case of LOAD and LEA, the destination register may be used for effective address computation. So, we can replace:

        LOAD    R5,R2,100

With the optimized sequence:

        LIS     R5,100
        PLUS    R5,R2
        LOADS   R5,R5

Macro assemblers supporting the Sparrowhawk should provide macros for all of the Hawk instructions, providing a second avenue to virtualize the Hawk instruciton set on the Sparrowhawk. Note that because many of the macros on the sparrowhawk take more space in the instruction stream, code that assembles correctly on the Hawk will not always assemble correctly on the Sparrowhawk. On the other hand, code developed under the constraints of this macro package on the Sparrowhawk will assemble correctly on the Hawk and make good use of the improved performance of that machine.