The Ultimate RISC paper presents the following bus for the Ultimate RISC:
Data, 16 bits, bidirectional tristate =================== Address, 16 bits, from IEU =================== Write, 1 bit, unidirectional ------------------- Read, 1 bit, unidirectional -------------------A pulse on the write line transfers data to the attached memory or register if the address matches the address for that memory.
When the read line is high, the contents of the addressed memory or register are transferred to the data line.
A single register R at address A on the ultimate RISC bus would look like the following:
Data, 16 bits =========================o======o===
Address, 16 bits ===o=====================|======|===
Write, 1 bit, ---|----o----------------|------|---
Read, 1 bit, ---|----|-o--------------|------|---
__|__ | | ___ | |
| = A | | --|AND|-------|-----/_\
address |_____| | --|___| | |
decoder | | | | |
----|-o | |
| | ___ ___|___ |
| --|AND|---|> R | |
----|___| |_______| |
| |
------
An output only centronics printer interface (an IBM PC compatable parallel port) would look like the following:
Data, 16 bits =========================o======o===
Address, 16 bits ===o=====================|======|===
Write, 1 bit, ---|----o----------------|------|---
Read, 1 bit, ---|----|-o--------------|------|---
__|__ | | ___ | |
| = A | | --|AND|-------|-----/_\
address |_____| | --|___| | |
decoder | | | | |
----|-o | _|_
| | ___ ___|___ | | 5
| --|AND|---|> R | | --/-|
----|___| |_______| o--/---| printer
| | 8 | connector
| |-/_\ |
--|--|---/--|
|-- 4
The printer or other device attached to the I/O interface
is responsible for interpreting the signals from the host
computer, but the following interface documentation gives
typical interpretations:
__ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __
output |\/|\/|OE|\/|SL|IN|LF|ST| | | | | | | | |
|__|__|__|__|__|__|__|__|__|__|__|__|__|__|__|__|
unused| | | control | data out |
OE -- enable tri-state driver for data to connector
SL -- select output to device
IN -- initialize device
LF -- control a device option (linefeed on printer)
ST -- strobe to device
__ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __
input |BS|AK|PE|OL|ER|\/|\/|\/| | | | | | | | |
|__|__|__|__|__|__|__|__|__|__|__|__|__|__|__|__|
status | unused | data in |
BS -- device busy
AK -- device acknowledges strobe pulse
PE -- out of paper
OL -- device on line
ER -- device error
The designer of the interface is completely uninterested in
all of the inputs and outputs other than the OE line. The
designer of the printer itself and the designer of the software
to control the printer must, however, agree on the use of the
other lines. The definitions given above are compatable with
a large number of IBM PC parallel port interfaces, except that
the PC interface is based on 8-bit registers, with distinct
addresses defined for data in and data out to each.
This design allows something that Centronics didn't anticipate, but it is a feature common on PC compatables -- that is, the use of the parallel port data lines for both input and output.
If we have a 16 bit address bus, we have, at most, 64K of address space. Consider the following design of a 16K memory module for this bus:
Data, 16 bits =========================o=====o===
Address, 16 bits ===o=====================|=====|===
Write, 1 bit, ---|-------o-------------|-----|---
Read, 1 bit, ---|-------|-o-----------|-----|---
__|__ | | ___ | |
/|| | \ | -|AND|-----|----/_\
High (+5) ----- | | | -|___| ___|___ |
| | | ---- | | | 14 | in | |
R R | | ___ ------|-|-/-----|Addr | |
| | | -|EQU| ___ | | ___ | 16Kx16| |
-oS0o-|-o-|---|___|-|AND|-|-o-|AND|-|> | |
Low | ---|EQU|-|___| ---|___| |__out__| |
(0)-oS1o-o-------|___| | |
-----
This diagram shows the details (at an electrical level)
of the address decoder for a typical memory such as this.
The pair of equivalence gates (EQU) and the AND gate make
the comparison between the 2 most significant bits of the
address on the bus and the 2-bit value set on the switches
(or jumpers) S0 and S1. If the switch is closed (or the jumper
is present), the value input to the comparator is 0, while if
the switch is open (or the jumper has been cut) the value
is 1. An open switch allows the resistor R (usually a few
thousand ohms) to pull the input to the comparator up to
logic 1, typically 5 volts, while a closed switch short
circuits the input to logic zero, typically ground or 0 volts.
Many devices have option select or address select jumpers or switches that operate as outlined above.
A good design for a multi-register ALU for the ultimate RISC might be:
Data, 16 bits =============================o==o===
Address, 16 bits ===o=========================|==|===
Write, 1 bit, ---|-----o-------------------|--|---
Read, 1 bit, ---|-----|-o-----------------|--|---
__|___ | | ___ | |
/| | |\ | -|AND|-----------|-/_\
_|_ | | | -|___| -----|--o
|=X || | | | 4 ___|___ | |
|___| -|--|-|-/-----|Addr | | |
| | | | ___ | | | |
----|--|-o-|AND|-|>16x16 | | |
| ---|___| |__out__| | |
| |_____| |
| |a b| |
| 4 | ALU | |
------/--------|f | |
|_f(a,b)| |
| |
-----
The minimum necessary set of ALU functions is:
The decision to use 16 registers in this ALU was arbitrary, but it is based on the fact that there are many successful 16 register machines.