A device may request an interrupt when it finishes an input/output transfer or reaches a similar ready condition. Typically, each device has a device specific interrupt-enable flipflop that must be set to allow the device to post the request; in addition, the CPU contains a global interrupt-enable flipflop that must be set to allow the CPU to respond to an interrupt.
When the CPU accepts an interrupt request, the effect is as if a
JMS instruction was executed to memory location 00000 (word
zero fo field zero). Thus, the 12 bit return address is stored in location
zero, and execution begins at location one.
In addition to the transfer of control, the global interrupt enable flipflop is reset when an interrupt occurs. If the extended memory option is present, the interrupt buffer is loaded with a record of the memory management state prior to the interrupt, and then both IF and DF are set to zero.
It is up to the interrupt service routine to save and restore all registers other than the PC, which was automatically saved in location zero. In addition, it is up to the program to determine which device requested an interrupt and either service or disable that device's interrupt request.
Under OS/8 (prior to OS/78 and OS/278), the system did not run with interrupts enabled, but individual applicatons could enable interrupts. By convention, it was expected that, on entry to or exit from an application, all devices would be either ready or would soon become ready (after completing an operation). That is, it was expected that all devices would either have done flags set to indicate operation completion, or they would be busy with an operation still in progress.
Thus, under OS/8, the handler for any device typically begins by checking to see if the previous operation was done before initiating a new operation. If an application enables interrupts, all devices will typically immediately request interrupts, and the interrupt handlers must either give the devices work to do or somehow turn off their done flags because no work is available for that device. Prior to exit, such an application would typically disable interrupts and then issue any device commands needed to get all devices to raise their done flags.
Only two interrupt management instructions are universally available
on all PDP-8 models,
IOF. All other
interrupt management instructions are system specific, although the
large majority are uniformly supported by all models after the PDP-8/E.
All instructions that deal with this option are privileged, and the detection and trapping of privileged instructions, if supported, is supported by the Time-Share option that is implemented as a subsystem of some PDP-8 memory management units.
SKONis used to test the state of the interrupt enable flipflop. If interrupts are enabled, the next instruction in sequence is skipped.
SKON is only available on the PDP-8/E and later models.
On earlier models, this was a no-op.
IONis used to turn on interrupts. The effect of this instruction is delayed one instruction so that, for example, an ION instruction immediately before a return instruction will not take effect until the return instruction is executed.
IOFis used to turn off or disable interrupts. The effect of this instruction is immediate. In addition, interrupts are disabled immediately when an interrupt occurs.
SRQis used to test whether there is a pending interrupt request. If a request is pending, the next instruction in sequence is skipped. This test is only meaningful when interrupts are disabled; it may be used, for example, to avoid the expense of an unnecessary return from interrupt when some device other than the one just serviced is also requesting service.
SRQ is only available on the PDP-8/E and later models.
On earlier models, this was probably interpreted as a nondeterministic
microcoded combination of
GTFis similar to
RIB, but is only available on the PDP-8/E and later models. This opcode was used for the Type 189 Analog to Digital Converter option on the original PDP-8, so it can cause very strange results if executed on the wrong machine!
GTF loads the accumulator with various information that may
need to be saved and restored during interrupts. This includes the link
bit, the state of the optional memory management unit, and the greater-than
flag from the optional extended arithmetic unit. These are packed into
the accumulator in the following format:
00 01 02 03 04 05 06 07 08 09 10 11 ___________________________________ | | | | | | | | | | | | | |__|__|__|__|__|__|__|__|__|__|__|__| | | | | | | | | | LINK GT IR II IE U IF DF
SGTinstruction supported by the extended arithmetic element.
SRQ. This is set to one if an interrupt requesting is pending.
IONand reset by the
IOFinstructions. This is set to one if interrupts are enabled.
RTFrestores the state of the flags that are saved by the
GTFinstruction, using the same data format. This instruction is only available on the PDP-8/E and later models; it can cause strange results when used on earlier machines (possibly acting as a microcoded combination of
RTF ignores the IR (interrupt request) bit that was saved by
GTF, and the IE (interrupt enable) bit is not fully restored
until the instruction after the
RTF instruction, so that
a return from interrupt may be executed before the next interrupt request
SGTis only supported if the extended arithmetic element is present, and then, only on the PDP-8/E and later machines. This instruction skips if the greater than flag is set.
CAFis only supported if the PDP-8/E and later machines. The effect of the CAF instruction is identical to a master clear issued from the front panel. AC and LINK are cleared, interrupts are disabled globally, and all I/O devices are reset. Generally, resetting a device sets the device specific interrupt enable bit and terminates any ongoing I/O activity. Resetting a device may initiate long reset and self-test sequences, and it may leave the device in an odd state, for example when a reset is issued in the middle of a write operation.
RTFinstructions are available, interrupt entry and exit can be quite complex, involving multiple instructions to save and restore the accumulator, link, multiplier quotient and step counter. Furthermore, interrupt dispatching, determining which device requested an interrupt, can be difficult because the PDP-8 provides nothing analogous to vectored interrupts.