The CDC 6600
Control Data Corporation had its origins in Engineering Research Associates, a contract research and development corporation born shortly after World War II. ERA developed the 1103 computer, a 36-bit machine that can claim to be the first stored-program to be sold commercially. Remington Rand Corporation bought ERA in 1952. For brief period, ERA competed with Remington Rand's other computer division, the Eckert-Mauchley Computer Corporation (manufacturers of the UNIVAC).
In 1955, Remington Rand merged with Sperry Corporation (the former Sperry Gyroscope) to form Sperry Rand. The new company merged the two computer companies to form Sperry UNIVAC -- the 1103 became the first in a series of UNIVAC 1100 series machines. A group of employees who had come to Sperry Rand from ERA were not happy with the big company environment and left in 1957 to found Control Data Corporation.
Sperry UNIVAC had offices in St. Paul Minnesota, and CDC's first corporate home was just across the river in Minneapolis. The new company was run by William Norris, and their chief computer architect was Seymour Cray. CDC's first computer, the CDC 1604, was a transistorized reimplementation of the ERA 1103, released in 1960. The 12-bit CDC 160 was released the same year, based on the same logic technology.
Cray began work on the 6600 shortly after finishing the design work for the first CDC computers, aiming at building a machine 50 times faster than the 1604. The design work on this new computer took long enough that CDC's corporate management began to meddle in the project, and in 1962, Cray demanded an arms-length relationship. Deveopment work on the 6600 was moved to Chippewa Falls Wisconsin, and higher levels of management were shut out while the machine design was completed.
Apparently, the Chippewa Falls operation developed the machine with 34 people on staff, including clerical and maintenance workers. This is a clear demonstration that a small carefully picked staff, freed from pressure from above and given time, can outproduce a huge well-funded bureaucratic development operation. IBM was very upset by this.
The result was spectacular, the fastest computer on earth, and its successors continued to hold that title for a decade. The 6600 family came to market in 1965, with a range of machines (6400, 6500, 6600). The first delivery was in 1965, to CERN in Geneva Switzerland (then and now, an important international particle-physics lab).
CDC's pricing philosophy for the 6600 was based on the assumption that not many would be made (in fact, over 100 were made) and therefore, the price could be very high. At first, these machines were primarily sold to government weapons labs and similar customers with very deep pockets. Eventually, larger universities began acquiring them as well.
The successor to the 6600 was the 7600, released in 1969 and holding the title of fastest computer in the world until 1975. It was not fully compatable at either the assembly language or object code level. Both used a 60 bit word with word addressable core memory, however, and except for speed, both were extremely similar in overall architecture.
The 6600 was the first machine to be designed where anything resembling pipelined execution was used. It was not, however, a pipeline in the modern sense, but rather, a set of cooperating functional units, each specialized to perform one type of computation. If consecutive instructions used different functional units and did not have operand dependencies, they could be executed in parallel. The CDC manual explains this nicely.
Where IBM designed special-purpose channel processors to handle I/O, CDC used a cluster of minicomputers, called peripheral processors. While these were not actual CDC 160 processors, they were largely software compatable with the CDC 160.
In fact, CDC's peripheral processor cluster for the CDC 6600 was itself an innovative design. In modern terms, it was not really a cluster of 10 separate processors, but rather, a single multithreaded processor that used just one ALU to execute 10 independent instruction streams. CDC described this architecture as a barrel processor because of the way a 10-bit shift register was used for each bit of each CPU register. The CPU would execute one instruction, and then shift the "barrel" one bit before executing the next instruction. After 10 instruction cycles, it was back to the first instruction stream.