The Digital Equipment Corporation PDP-8
Memory Management Instructions
the PDP-8 Programmer's Reference Manual
All instructions that deal with this option are privileged, and the detection and trapping of privileged instructions, if supported, is supported by the Time-Share option that is implemented as a subsystem of some PDP-8 memory management units; this is discussed separately because this option is generally disabled except in systems intended for supporting timesharing applications.
00 01 02 03 04 05 06 07 08 09 10 11 ___________________________________ | 1| 1| 0| 0| 1| 0| | | | | | | |__|__|__|__|__|__|__|__|__|__|__|__| | | | | | Opcode | Field | Op |Formally, all memory management instructions are IOT instructions involving devices 20 through 27. The least significant 3 bits of the device address (bits 6 - 8) are used to specify the memory field, for those instructions where this must be specified, while the least significant 3 bits of the instruction specify what operation to perform.
On the PDP-8/A, the KT8AA option supports addressing of up to 128K words of memory. This is fully compatable for the low 32K only.
Bits 6 through 8 of the instruction word are stored in the data field register. There is no effect on the accumulator or link bit. Self-modifying code must be used to change to a variable field.
It is legal to microcode
CIF to make a single instruction
that sets both DF and IF. Some assemblers provide the mnemonic
CDI for this.
Bits 6 through 8 of the instruction word are stored in the Instruction Buffer (IB) register. There is no effect on the accumulator or link bit. Self-modifying code must be used to change to a variable field.
The instruction buffer register is a 3 bit register instide the memory
management unit. The contents of this register are transferred to IF,
instruction field register, whenever a
instruction is executed.
CIF instruction disables interrupts until the next
branch instruction is executed. This involves a special interrupt control
flipflop distinct from the ones controlled by the
RDFors the DF register with bits 6 to 8 of the accumulator. The other bits of the accumulator are unaffected. This instruction is commonly used to construct a
CIFinstruction as follows:
CLA TAD (CDF) / load field setting instruction RDF / make it ref current data field DCA CDFLOC / self-modify the program
RIFors the IF register with bits 6 to 8 of the accumulator. The other bits of the accumulator are unaffected. This instruction is commonly used to construct a
CIFinstruction as illustrated with the
RIBors the Interrupt Buffer register with the least significant bits of the accumulator. The Interrupt Buffer register is used to save the the state of the memory management unit when an interrupt occurs. This register is either 6 or 7 bits, depending on whether the machine is equipped with the time-share option:
00 01 02 03 04 05 06 07 08 09 10 11 ___________________________________ | | | | | | | | | | | | | |__|__|__|__|__|__|__|__|__|__|__|__| | | | | | U| IF | DF |
RMFrestores the memory management unit to its state at the time of the last interrupt. This involves the transfer of the contents of the Interrupt Buffer to the IB and DF registers. (note that the IB register is copied into the IF register when a JMP or JMS instruction is executed.) If the time-share option is present and enabled, this also involves restoring the state of the user-mode bit.
RMF instruction does not restore the IF register
directly, but rather, it restores the IB register, so that the change
of instruction field is deferred until the next branch instruction.
Thus, interrupts must be disabled between the
the following branch, usually the return from interrupt. This is
exactly the same restriction as applied to the use of the
RMF instruction should not be used in the context of
systems where one interrupt service routine may interrupt another.
In that context, an
RIB instruction must precede the
interrupt enable within the low-priority interrupt service routine,
and, at the end of the low-priority routine, a sequence of
instructions must be used to restore the state.
FIELD FIELD 3
FIELD directive in the PAL family of absolute PDP-8
assemblers is used to set the memory field to which code is to be
assembled. If this directive is not used, assembly defaults to field
zero. If used without an operand, it forces the location counter to
advance to the next field. If used with an operand between 0 and 7,
it forces assembly to begin at the start of that field or at location
0200 of that field (depending on the version of the assembler).
CDFinstruction needed to set the high 3 bits of the address of the data.
Given a variable
X at address 54321 (word 4321 of field 5),
the following code directly references
CDF 50 TAD I (4321)A pointer to location
Xmight be constructed as follows
XPT, CDF 50 4321The following code uses this pointer:
CLA TAD XPT / get the CDF instruction DCA .+1 / self modify CDF .-. / -- modified location -- TAD I XPT+1 / fetch word from remote field
In the following example, it is assumed that the assembly-time
CURFLD contains the identity of the current
memory field (between 0 and 7). Note that the
operator is the standard symbol for multiplication in the PAL
family of assemblers.
PROCF= CURFLD^8 / argument to CDF to call PROC PROC, .-. / entry point CLA RDF / find out where call was from TAD (CIF CDF) / make CDI for return DCA PROCR / self modify ... PROCR, CIF CDF .-. / -- modified location -- JMP I PROC / returnA call to the above procedure would take the following form:
CIF PROCF / setup for call JMS I [PROC] / call
Note that, on entry to this procedure, the current data field refers to
the caller's instruction field; this makes parameter passing easy because
it forces all indirect references to the caller's address space. If the
procedure makes any indirect references to other material in its own
address space, or if it makes any far-calls to other procedures, they
must be preceded by