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The Digital Equipment Corporation PDP-8

Microcoded Instructions

Part of the PDP-8 Programmer's Reference Manual
by Douglas W. Jones
THE UNIVERSITY OF IOWA Department of Computer Science

Index


There are three groups of microcoded instructions on the PDP-8; all begin with the opcode 111, and all execute in a single cycle.

Group One Microcoded Instructions

            00 01 02 03 04 05 06 07 08 09 10 11
            ___________________________________
           | 1| 1| 1| 0|  |  |  |  |  |  |  |  |
           |__|__|__|__|__|__|__|__|__|__|__|__|
                       |CLA   CMA   RAR   BSW
                           CLL   CML   RAL   IAC

                         1  1  2  2  4  4  4  3

All of the microcoded instructions in group one operate on the accumulator and link. The numbers under the mnemonic for each instruction give the order in which they are applied.

7200 - CLA Clear Accumulator

CLA sets each of the 12 bits of the accumulator to zero, prior to any other microcoded operations.

7100 - CLL Clear Link

CLL sets LINK (the link bit) to zero, prior to any other microcoded operations.

7040 - CMA Complement Accumulator

CMA complements each of the 12 bits of the accumulator. If used in conjunction with CLA, this sets all 12 bits of the accumulator to one.

7020 - CML Complement Link

CML complement LINK (the link bit). If used in conjunction with CLL, this sets the link bit to one.

7001 - IAC Increment Accumulator

IAC increments the 13 bit LINK/AC register. Used with CMA, this computes the 2's complement. Used with CLA, this loads the constant 1.

7010 - RAR Rotate Accumulator Right

RAR rotates (circularly shifts) the 13 bit LINK/AC register one place right, so that the least significant bit of AC becomes the new link, and the old link becomes the most significant bit of AC.

On the PDP-8/I and later models, shift operations are executed after all other microcoded operations in. Prior to the PDP-8/I, shift operations were executed at the same time as IAC; portable code should assume the latter.

7004 - RAL Rotate Accumulator Left

RAL rotates (circularly shifts) the 13 bit LINK/AC register one place left, so that the most significant bit of AC becomes the new link, and the old link becomes the least significant bit of AC.

On the PDP-8/I and later models, shift operations are executed after all other microcoded operations in. Prior to the PDP-8/I, shift operations were executed at the same time as IAC; portable code should assume the latter.

7012 - RTR Rotate Twice Right

RTR is equivalent to two consecutive RAR instructions. It is encoded by setting the BSW bit, 0002 in addition to the RAR bit.

7006 - RTL Rotate Twice Left

RTL is equivalent to two consecutive RAL instructions. It is encoded by setting the BSW bit, 0002 in addition to the RTR bit.

7002 - BSW Byte Swap

BSW exchanges the high 6 bits of AC with the low 6 bits of AC, after any clear, complement or increment operations. This operation is only supported by the PDP-8/E and later models. For this reason, it should be avoided in portable code. Note that microcoding BSW with RAR or RAL will produce RTR or RTL.

Group Two Microcoded Instructions, Or Group

            00 01 02 03 04 05 06 07 08 09 10 11
            ___________________________________
           | 1| 1| 1| 1|  |  |  |  | 0|  |  | 0|
           |__|__|__|__|__|__|__|__|__|__|__|__|
                       |CLA   SZA
                           SMA   SNL

                         2  1  1  1

Group two microcoded instructions allow conditional tests to be made on the LINK/AC. These are divided into the or group and the and group. In the or group, microcoding multiple instructions results in a test for the logical or of the indicated conditions.

7600 - CLA Clear Accumulator

The accumulator may be cleared after any test performed by a group two instruction. Unless microcoded with other group two instructions, PDP-8 assemblers generally assume that the CLA mnemonic refers to the group one instruction!

7500 - SMA Skip if Minus Accumulator

SMA skips the next instruction (increments the program counter) if the accumulator is negative (the sign bit of the accumulator is one).

7440 - SZA Skip if Zero Accumulator

SZA skips the next instruction (increments the program counter) if the accumulator is zero (all bits of the accumulator are zero).

7420 - SNL Skip if Nonzero Link

SNL skips the next instruction (increments the program counter) if LINK (the link bit) is not zero.

Group Two Microcoded Instructions, And Group

            00 01 02 03 04 05 06 07 08 09 10 11
            ___________________________________
           | 1| 1| 1| 1|  |  |  |  | 1|  |  | 0|
           |__|__|__|__|__|__|__|__|__|__|__|__|
                       |CLA   SNA
                           SPA   SZL

                         2  1  1  1
Group two microcoded instructions allow conditional tests to be made on the LINK/AC. These are divided into the or group and the and group. In the and group, microcoding multiple instructions results in a test for the logical and of the indicated conditions.

7610 - CLA Clear Accumulator

The accumulator may be cleared after any test performed by a group two instruction. Unless microcoded with other group two instructions, PDP-8 assemblers generally assume that the CLA mnemonic refers to the group one instruction!

7510 - SPA Skip if Positive Accumulator

SPA skips the next instruction (increments the program counter) if the accumulator is not negative (the sign bit of the accumulator is zero).

7450 - SNA Skip if Nonzero Accumulator

SNA skips the next instruction (increments the program counter) if the accumulator is nonzero (any bit of the accumulator nonzero).

7430 - SZL Skip if Zero Link

SZL skips the next instruction (increments the program counter) if LINK (the link bit) is zero.

Privileged Group Two Microcoded Instructions

            00 01 02 03 04 05 06 07 08 09 10 11
            ___________________________________
           | 1| 1| 1| 1|  |  |  |  | 1|  |  | 0|
           |__|__|__|__|__|__|__|__|__|__|__|__|
                       |               OSR
                                          HLT
The privileged group two microcoded instructions will cause an interrupt if they are executed in user mode on a PDP-8 equipped with the time-share option (KM8-E or equivalent). This interrupt is delivered after any skip or clear operations that may be microcoded with it, and as a result, the interrupt service routine may be unable to determine which instruction caused the interrupt; therefore, programs intended to operate compatably under time-shared PDP-8 environments should not microcode skip operations with these instructions!

7404 - OSR Or Switch Register

OSR ors the contents of the front-panel switch register with the contents of the accumulator. The microcoded combination CLA OSR loads the switch register into the accumulator.

In time-shared environments, the timesharing monitor typically maintains an emulated switch register for each user, and software emulation routines called by the time-share interrupt hardware duplicate the OSR function using this emulated switch register.

7402 - HLT Halt

HLT halts the processor after the completion of the current instruction.

In time-shared environments, the timesharing monitor typically interprets a HLT instruction as a request for a return to the command language interpreter.

Group Three Microcoded Instructions

            00 01 02 03 04 05 06 07 08 09 10 11
            ___________________________________
           | 1| 1| 1| 1|  |  |  |  |  |  |  | 1|
           |__|__|__|__|__|__|__|__|__|__|__|__|
                       |CLA   SCA   \_    _/
                       |   MQA   MQL  CODE

                         1* 2  2  2     3
On all models of PDP-8 prior to the PDP-8/E, the group three instructions were only implemented if the EAE option was present. If this option is absent on such machines, all group three instructions become no-ops.

On the PDP-8/E and following models, CLA, MQA and MQL instructions are implemented in the standard CPU, while the other operations are implemented in the optional EAE. Portable code should avoid relying on the availability of any of these instructions.

The CODE field and the SCA bit only function if the EAE is present; these should be zero unless specific EAE instructions are intended. These are documented elsewhere.

7601 - CLA Clear Accumulator

The accumulator may be cleared prior to other group three microcoded operations. Unless microcoded with other group three instructions, PDP-8 assemblers generally assume that the CLA mnemonic refers to the group one instruction!

7501 - MQA or Multiplier Quotient with Accumulator

MQA ors the contents of the MQ register into AC. Usually, the microcoded combination CLA MQA is used; this first clears the accumulator, so the result can be viewed as a load operation.

7421 - MQL Multiplier Quotient Load

MQL loads the contents of the MQ register from AC and then clears AC.

The microcoded combination CLA MQL first clears AC, so the result is to clear both AC and MQ. Some assemblers supply the mnemonic CAM for this combined operation.

The microcoded combination MQA MQL swaps the contents of AC and MQ. Some assemblers supply the mnemonic SWP for this combined operation.

Macros

The PDP-8 instruction set is so small that many operations that are usually single instructions on a larger machine must be composed from simpler instruction sequences on the PDP-8. While these are referred to as macros here, the memory resources of the PDP-8 are limited enough that these are usually not coded as given, but rather, carefully folded into other computations.

Two's Complement

To two's complement a number, take it's ones complement and then increment.

TCA=    CMA IAC

This is a single microcoded machine instruction, and it is equally common to find it written out long-hand or defined as shown here so it can be used with a single short mnemonic.

Skip if Less than or Equal to Zero

        SMA SZA

This is a single microcoded instruction from the Group Two Or Group, so in one cycle, it skips if the accumulator is negative or zero.

Skip if Greater than Zero

        SPA SNA

This is a single microcoded instruction from the Group Two And Group, so in one cycle, it skips if the accumulator is positive and nonzero.