Assignment 5, due Feb 29

Part of the homework for 22C:112, Spring 2008
by Douglas W. Jones
THE UNIVERSITY OF IOWA Department of Computer Science

Always, on every assignment, please write your name legibly as it appears on your University ID and on the class list! All assignments will be due at the start of class on the day indicated (usually a Friday). The only exceptions to this rule will be by advance arrangement unless there is what insurance companies call "an act of God" - something outside your control. Homework must be turned in on paper and in class! Late work may be turned in to the teaching assistant's mailbox, but see the late work policy. Never push late work under someone's door!

  1. Background: On a simple DMA disk interface, you would write the sector, track and cylinder addresses to the corresponding device addresses, then write the starting memory address and word count to the DMA control regisers before writing the disk command that starts the transfer. This involves a minimum of 6 write operations to device registers.

    Now, consider a system based on a bus architecture comparable to the SCSI bus. On this system, the bus controller has memory-address, word-count and control registers for the DMA transfer, and a device-select register and a device-data register to communicate directly with devices on the bus. To write to an interface register of a particular device on the bus, the program must first select a device register using the bus device-select register, then write the command to that device using the bus device-data register.

    Question: Give the program of write operations to device registers required to start a disk operation on the bus-structured disk interface. Group these operations into 6 groups so that each group corresponds to one of the 6 write operations required to start a transfer on the simple disk interface, and document each group accordingly. (0.5 points)

  2. Background: Some low-performance systems do not have direct-memory-access controllers. On those, the disk transfer typically moves data to a dedicated buffer, sometimes called the silo. The silo address register is typically set to zero by assignment to the command register, and data can be read from or written to consecutive words of the silo by reading or writing the silo data register. During a disk read or write operation, this mechanism is used to transfer data between the silo and disk, while if the program issues a no-op command to the disk, this mechanism can be used to transfer data between the computer and the disk.

    a) Outline the code to do a disk-read operation, reading the addressed sector (cylinder, sector, surface) to the user's buffer (address, length). Assume no interrupts, so the program must wait for the ready bit by polling. (0.5 points)

    b) Discuss and evaluate the options for using interrupts with this disk system. Consider, for example, the relative merits for an interrupt that signals "disk transfer done" versus an interrupt signalling readyness to transfer a single byte between the silo and the user's memory, and consider the question of whether silo-user data transfers belong in an interrupt service routine or in interruptable user-level code. (0.5 points)

  3. Background Most modern disk drives incorporate an onboard cache, so when you write to the disk, data is coped to the cache immediately (if there is space), and when you read from the disk, there may be no nead to actually read the disk itself if the desired data is currently available in the cache.

    a) If a disk drive has an onboard cache, is there any need to do disk scheduling? If so, where? (0.5 points)

    b) Design an experiment that a disk user could use to determine empirically the size of the on-board cache on a disk drive. Assume that the operating system has no disk-cache or that any cache behavior in the operating system has been turned off. (0.5 points)

    c) Is there any way a disk user could measure the difference between a software disk cache implemented by the operating system and a hardware disk cache implemented by the disk controller? If not, why? If so, how? (0.5 points)