Douglas W. Jones
Assume that each vertex has a unique id, and that each vertex has a local table of neighbors, call it N[i] giving the neighbors of the vertex (i is the index in the table, running from 1 to neighbors, so there is one table entry for each neighbor). The operation send(m,N[i]) will send the message m to the ith neighbor of this vertex. The operation receive(m,i) will block awaiting a message. When the message is received, it is stored in buffer m, and the index i of that neighbor in the receiver's neighbor table N is also returned.
All messages are tuples
Assume that each vertex runs the following top-level code:
The Problem, part A: What message types are involved in the election
algorithm, and for each type, what fields are required. Assume that multiple
overlapping elections must be detected if they occur, and that overlaps will
be resolved by the cancellation of the election originated by the vertex
with the lower id.
The Problem, part B: Write pseudocode for initiate election and
for process_election_message.
In this question, we are not interested in any I/O devices, but are concerned
only with data residing in memory. All synchronization between the 2 CPU's
uses busy waiting and algorithms such as Dekker's. Access to individual
memory locations is atomic.
Part A: What concepts from our discussion of atomic transactions are
applicable to this system and what concepts are inapplicable.
Part B: Propose an atomic transaction implementation appropriate for
this system.
repeat
if detect failure
initiate_election()
else
receive(msg,m)
if msg.type = election
process_election_message(msg,i)
else
process_normal_message(msg,i)
endif
endif
forever
You can assume that process_normal_message has something to do with the
application.
M1
____|_____ Bus 1
| |
M-CPU CPU-M
|__________|
| Bus 2
M2
In this system, each CPU and each memory module has its own power supply,
and the busses are passive and carry no power. Local memory on each CPU
is used for code and local variables, so the shared memory modules are used
only for shared data. The address space of each CPU is divided into 3
segments, Mlocal, M1 and M2.