Homework 4

22C:116, Fall 1997

Due Friday Sept. 19, 1997, in class

Background Consider the following MMU interface:

The MMU has Stlb registers, named tlb[0] to tlb[Stlb]. Each register has the following format:
```
         ____________ _____________ ________
        |____________|_____________|________|
        | pagenumber | framenumber | rights |
```
The pagenumber and framenumber fields are fields of the virtual and physical address, respectively. the rights field may have values of either no-access, read-only or read-write.
The MMU also has a register named va that holds the virtual address that caused the most recent page fault, and a register named op that holds the operation attempted (fetch or store) at the time of the most recent fault.
Any Translation Lookaside Buffer register may hold entries for any virtual address (this is not a realistic assumption -- real systems usually restrict this!).
All questions of the organization of the page and frame tables are matters for the software.
Main memory consists of Frames page frames, where Frames > Stlb.
All questions of the organization of the page and frame tables are matters for the software.

Homework Assignment

Given the above assumptions, outline an appropriate data structure for the virtual address map (page table) and frame table, with the intent that this data structure support modified clock replacement with software management of both mark and dirty bits. Assume that your entire data structure can be maintained in main memory!

Given your answer to the above question, outline (in detailed pseudocode) the page fault handler you would use.

Discuss how you would modify your answers to the above questions if the virtual address map was so large that it was not practical to fit the address map entirely in main memory.

Assuming your system has multiple processes, and that you wish to run one process while disk I/O for page faults of another process takes place, outline how the scheduler, page fault handler and process manager would interact during the processing of one page fault. That is, what process state changes take place, what code initiates these state changes, and how would you expect the system components to interact.