Machine Problem 4, due Apr. 1

Starting Point: Start with the posted solution to MP3. Add to it the code for class Simulation distributed with the lecture notes for March 8. Put the code for Simulation right after class ScanSupport and before class Gate.

Aside from the header comment on the entire file, which must have your name and section, you shoul make no changes to classes Errors ScanSupport or Simulation. Within the code for gates and wires, most of your changes will involve adding new simulation methods and perhaps changes that are consequences of these.

As usual, add a JavaScript @author tag to each class you modify giving your name and update the @version tag to give the date of your modification.

Specific New Requirements: Make the logic simulator actually simulate the digital logic, with the following behaviors:

• The simulation should only run if there were no warnings issued during the building of the model.

• The initial values of all gate outputs should be zero (that is, false), with one exception: The initial value of the output of an input gate should be whatever is specified by the declaration of that gate.

• The initial values of all wire outputs should be zero (that is, false), and this implies that the initial values of all inputs to gates can be assumed to be zero.

• For any wire connected to an initially one (true) source, an initial ouput change event should be scheduled for that wire's destination after that wire's delay.

• For any input gate with a change count greater than zero, an initial output change event should be scheduled for that gate's output after that gate's delay. More changes may be scheduled at or after initialization if the change count is greater than one.

• All logic gates must compute or recompute their appropriate output value whenever an input changes, and if the result is a change in their output, that change must be delivered to each outgoing wire.

• Output a trace of all changes to the outputs of wires and the outputs of gates, as they occur to System.out. The trace should show the time, the change in the form old->new and the gate or wire that changed.

Consider the following example circuit:

gate a input 1 1.0 2
gate b output
wire a 0.1 b

Here is an appropriate simulation output:

time 0.1 0->1 wire a 0.1 b
time 1.0 1->0 gate a input 1 1.0 2
time 1.1 1->0 wire a 0.1 b
time 2.0 0->1 gate a input 1 1.0 2
time 2.1 0->1 wire a 0.1 b

This trace is a debugging trace, totally inappropriate for simulations of any complexity, but very useful in seeing what is going on in very small models.

We do not recommend trying logic circuits with more than one or two real gates using this output format.