Machine Problem 3, due Oct 26

Part of the homework for CS:2820, Fall 2015
by Douglas W. Jones
THE UNIVERSITY OF IOWA Department of Computer Science

Extending MP2: Consider the posted solution to Machine Problem 2. This solution is only the first step on the road to a working logic simulator.

Event routines: For each member of the class Gate and Wire, add appropriate event service routines to handle the propagation of logic changes through the logic circuit. For wires, any change of the input should be transmitted to the output after the wire's delay. For gates, if an input changes in a way that would change the output, the output change should occur after the delay of that gate.

In order to see if the gate's output should change, each gate will need to keep, on hand, an array of the values of its current inputs and the value of its current output. Initially, all inputs should be zero (false) and the outputs should be (false), and then, if this is inconsistant with the gate's rules, the gate should immediately schedule an output change event.

The Event Set: You will need to create an event-set mechanism that allows new events to be scheduled and that organizes these events sequentially by time.

Simulation: Where the main program for MP2 ended with printing the logic circuit to standard output, the new main program should simulate the logic circuit. For debugging, at this point, simply have each gate print out its output change whenever it changes. For example:

     Time 4.6 Gate X changes to true.
     Time 4.9 Gate Y changes to false.
     Time 9.8 Gate X changes to false.

Simulation Control: For debugging purposes, the simulation ought to run until the pending event set is empty and then terminate. The model we use to test your simulation will terminate. Here is a model that never terminates:

     gate not X 0.1
     wire X X in 0.9

The above model will oscillate forever, with the output of gate X changing every 1 time unit. Here is a model that will terminate:

     gate and A 0.1
     wire A A in1 0.1
     wire A A in2 0.1

     gate not B 0.1
     wire A B in 0.1

     gate not C 0.1
     wire B C in 10.0

     gate and D 0.1
     wire B D in1 0.1
     wire C D in2 0.1

Explanation: Gate A has an output that is initially false and stays false forever. Gate B has an output that goes from false to true at time 0.1 and then stays true forever. Gate C has an output that goes from false to true after 0.1 time units, but then, at time 10.1, its input goes true, so at time 10.2, its output goes false. Gate D has an output that goes from false to true at time 0.2 and then goes false at time 10.3.

Grading criteria: Essentially the same criteria as for MP2

Submission: Your solution should consist of a single file, with one public method, main. (Later, we will chop the file into smaller more managable pieces.)

To submit your solution, make sure it is in a file called LogicCircuit.java (this requires that the main method be in a class called LogicCircuit. This must be in the current directory. Follow the usual submission instructions, but submit to mp3 instead of mp3.