# Iowa Logic Specification Language models to demonstrate
# advanced features and test the Iowa Logic Simulator.
# These are in the form of a UNIX shell archive.  Pipe it through sh
# (the Bourne Shell) to expand the library into useful form.

# If you're not on a UNIX system, create a directory named demo, then use
# a text editor to break this file into the separate files from which it
# was made.  Each text file is delimited by lines containing the string
# "xxxqzzqxxx" and each file should be named with the name appearing
# between the > and < marks on the line immediately before the text of
# that file.

if mkdir demo
 then
   echo    directory demo created.
 else
   echo    either a file or directory named demo already exists,
   echo    or you have no write access to the current directory.
   exit
 fi

chmod go+rx demo
cd demo

cat > README <<\xxxqzzqxxx
  Advanced Feature Demo for the Iowa Logic Specification Language
                               and
            Test Program for the Iowa Logic Simulator

                            Version 9

                                by
                         Douglas W. Jones
                        University of Iowa
                               1988

                        jones@cs.uiowa.edu

This directory contains 3 demonstrations of the advanced features in the
Iowa Logic Specification Language.  These demonstrations have also proven
to be decent tests of whether the Iowa Logic Simulator has been correctly
compiled.  Sadly, many Pascal compilers will silently generate incorrect
code for the Iowa Logic Simulator, and this can only be uncovered by
running the simulator!

All three demos are based on implementations of a generic decoder,
parameterized by the range of inputs; if there are n inputs in the range,
these have 2**n outputs, indexed in the range 0 .. (2**n)-1.  These
implementations differ in the way they generate the wiring of the decoder;
all may be tested with the same test data!

The files here are:

   README    -- this text

   direct    -- a direct iterative implementation of the generic decoder
   pattern   -- an iterative implementation based on repeating patterns
   recursive -- an implementation based on recursive decomposition

   test      -- a test script for these models
   testout   -- the expected output

To try one of the demos or test the logic simulator, run the logic
simulator, and when it prompts for an input file name, enter the name of
one of the implementations included here.  The logic simulator will then
print out a tally report on the resources consumed within the sumulator
and the number of subcircuits and primitive parts used to build the
decoder.  Following this, the simulator will give a simulation header
and prompt for simulation input.  Enter the command "r test" to force
the simulator to read from the test script included here, and then
compare the output with the testout file included here.

Copyright notice:  The author explicitly grants unlimited rights to copy,
modify, sell, or otherwise distribute copies of these six files, with no
strings attached!
xxxqzzqxxx
cat > direct <<\xxxqzzqxxx
tally circuit { direct } decode8;

	circuit decoder( range inrange );  -- designed by D. W. Jones
	{  a direct iterative design for a generic decoder with
	   each gate wired in turn.  The problem with this design is
	   determining which inputs to each decoding gate should be
	   inverted, given only the gate number and the input number. }
	range	outrange = 0..2**size(inrange) - 1;

	inputs	in(inrange);
	outputs	out(outrange);

	parts
		{ each input must be inverted }
		inv(inrange): not;

		{ gates to perform actual decoding }
		dec(outrange): and( size( inrange ) );

	wires
		{ invert the inputs }
		for i in inrange do
		    in(i) to inv(i).in;
		endfor;

		{ wire each decoding gate }
		for j in outrange do

		    { wire each input of the gate }
		    for i in 1 .. size(inrange) do
			if ( (j/2**(i-1)) mod 2 ) = 0 then
			    inv(i+first(inrange)-1).out to dec(j).in(i);
			else
			    in(i+first(inrange)-1) to dec(j).in(i);
			endif;
		    endfor;

		    { wire the output of the gate }
		    dec(j).out to out(j);

		endfor;
	end;

inputs	in2 in1 in0;
outputs out(0..7)
parts	dec: decoder(0..2);
wires
	in2 to dec.in(2);
	in1 to dec.in(1);
	in0 to dec.in(0);
	dec.out to out;
end.
xxxqzzqxxx
cat > pattern <<\xxxqzzqxxx
tally circuit { pattern } decode8;

	circuit decoder( range inrange );  -- designed by D. W. Jones
	{  An iterative implementation of a generic decoder taking
	   advantage of the repeating patterns as one scans down the
	   binary numbers in a given column. }
	range	outrange = 0..2**size(inrange) - 1;

	inputs	in(inrange);
	outputs	out(outrange);

	parts
		{ each input must be inverted }
		inv(inrange): not;

		{ gates to perform actual decoding }
		dec(outrange): and( size( inrange ) );

	wires
		{ invert the inputs }
		for i in inrange do
		    in(i) to inv(i).in;
		endfor;

		{ wire inputs of decoding gates }
		for i in 1 .. size(inrange) do
		    for jj in 0 .. size(outrange)/2**i - 1 do
			for j in jj*2**i .. jj*2**i + 2**(i-1) - 1 do
			    inv(i+first(inrange)-1).out to dec(j).in(i);
			endfor;
			for j in jj*2**i + 2**(i-1) .. (jj + 1)*2**i - 1 do
			    in(i+first(inrange)-1) to dec(j).in(i);
			endfor;
		    endfor;
		endfor;

		{ wire outputs of decoding gates }
		for j in outrange do
		    dec(j).out to out(j);
		endfor;
	end;

inputs	in(0..2);
outputs out(0..7)
parts	dec: decoder(0..2);
wires
	in to dec.in;
	dec.out to out;
end.
xxxqzzqxxx
cat > recursive <<\xxxqzzqxxx
tally circuit { recursive } decode8;

	circuit decoder( range inrange );  -- designed by D. W. Jones
	{  A recursive implementation of a generic decoder using the
	   decomposition of an n input decoder into two n-1 input
	   decoders with enable inputs and an inverter to select which
	   gets enabled. }
	range	outrange = 0..2**size(inrange) - 1;

		circuit	decode( integer n, m );
		inputs
			enable(1 .. m);
			in(1 .. n);
			inbar(1 .. n);
		outputs
			out(0 .. 2**n-1);
		parts
			if n < 1 then
			    error
			else if n = 1 then
			    dec(0 .. 1): and(n + m);
			else
			    code(0 .. 1): decode(n - 1, m + 1);
			endif
		wires
			if n = 1 then
			    for i in 0 .. 1 do
				for j in 1 .. m do
				    enable(j) to dec(i).in(j);
				endfor;
				dec(i).out to out(i);
			    endfor;
			    inbar(1) to dec(0).in(m + 1);
			    in(1) to dec(1).in(m + 1);

			else -- n > 1
			    for i in 0 .. 1 do
				for j in 1 .. m do
				    enable(j) to code(i).enable(j);
				endfor;
				for j in 0 .. 2**(n-1)-1 do
				    code(i).out(j) to out(i*2**(n-1) + j);
				endfor;
			    endfor;
			    for i in 1 .. n-1 do
				in(i) to code(0).in(i), code(1).in(i);
				inbar(i) to code(0).inbar(i), code(1).inbar(i);
			    endfor;
			    inbar(n) to code(0).enable(m + 1);
			    in(n) to code(1).enable(m + 1);
			endif;
		end { decode };

	inputs	in(inrange);
	outputs	out(outrange);

	parts
		dec: decode( size( inrange ), 0 );
		inv(inrange): not;
	wires
		for i in inrange do
		    in(i) to dec.in( i - first( inrange ) + 1 );
		    in(i) to inv(i).in;
		    inv(i).out to dec.inbar( i - first( inrange ) + 1 );
		endfor;
		dec.out to out;
	end;

inputs	in(0..2);
outputs out(0..7)
parts	dec: decoder(0..2);
wires
	in to dec.in;
	dec.out to out;
end.
xxxqzzqxxx
cat > test <<\xxxqzzqxxx
000
001
010
011
100
101
110
111
000
00p
0p0
0pp
p00
p0p
pp0
ppp
q
xxxqzzqxxx
cat > testout <<\xxxqzzqxxx
IOWA Logic Simulator, Ver. 9
Source file name: ----------
String pool occupies 320 bytes out of 8000 available.
Packed text occupies 431 bytes out of 16000 available.
Symbol table holds 65 entries out of 2303 available.

Tally of subcircuits:
    1 decoder  

Tally of parts used to build circuit:
    8 and          3 not      
======================================================================
   circuit name   = decode8
   input interval = 1.0us       If you need help, type h.
   output interval= 500ns
----------------------------------------------------------------------
TIME:OUTPUTS                              :INPUTS
----:-------                              :------
 500:out(  7)                             : in2
 ns : | : | : | : | : | : | : | :out(  0) : |in1
    : | : | : | : | : | : | : | : |       : ||in0
    : | : | : | : | : | : | : | : | :     : |||
======================================================================
   0:|  :|  :|  :|  :|  :|  :|  :|  :INPUT: r part.test
   0:|  :|  :|  :|  :|  :|  :|  :|_ :INPUT: 000
   1:|  :|  :|  :|  :|  :|  :|  :  |:     : 000
   2:|  :|  :|  :|  :|  :|  :|  :  |:INPUT: 001
   3:|  :|  :|  :|  :|  :|  :|_ : _|:     : 001
   4:|  :|  :|  :|  :|  :|  :  |:|  :INPUT: 010
   5:|  :|  :|  :|  :|  :|_ : _|:|  :     : 010
   6:|  :|  :|  :|  :|  :  |:|  :|  :INPUT: 011
   7:|  :|  :|  :|  :|_ : _|:|  :|  :     : 011
   8:|  :|  :|  :|  :  |:|  :|  :|  :INPUT: 100
   9:|  :|  :|  :|_ : _|:|  :|  :|  :     : 100
  10:|  :|  :|  :  |:|  :|  :|  :|  :INPUT: 101
  11:|  :|  :|_ : _|:|  :|  :|  :|  :     : 101
  12:|  :|  :  |:|  :|  :|  :|  :|  :INPUT: 110
  13:|  :|_ : _|:|  :|  :|  :|  :|  :     : 110
  14:|  :  |:|  :|  :|  :|  :|  :|  :INPUT: 111
  15:|_ : _|:|  :|  :|  :|  :|  :|  :     : 111
  16:  |:|  :|  :|  :|  :|  :|  :|  :INPUT: 000
  17: _|:|  :|  :|  :|  :|  :|  :|_ :     : 000
  18:|  :|  :|  :|  :|  :|  :|  :  |:INPUT: 00p
  19:|  :|  :|  :|  :|  :|  :|_ : _|:     : 000
  20:|  :|  :|  :|  :|  :|  : _|:|_ :INPUT: 0p0
  21:|  :|  :|  :|  :|  :|_ :|  : _|:     : 000
  22:|  :|  :|  :|  :|  : _|:|  :|_ :INPUT: 0pp
  23:|  :|  :|  :|  :|_ :|- :|- : _|:     : 000
  24:|  :|  :|  :|  : _|:|  :|  :|_ :INPUT: p00
  25:|  :|  :|  :|_ :|  :|  :|  : _|:     : 000
  26:|  :|  :|  : _|:|  :|  :|  :|_ :INPUT: p0p
  27:|  :|  :|_ :|- :|  :|  :|- : _|:     : 000
  28:|  :|  : _|:|  :|  :|  :|  :|_ :INPUT: pp0
  29:|  :|_ :|  :|- :|  :|- :|  : _|:     : 000
  30:|  : _|:|  :|  :|  :|  :|  :|_ :INPUT: ppp
  31:|_ :|- :|- :|- :|- :|- :|- : _|:     : 000
  32: _|:|  :|  :|  :|  :|  :|  :|_ :INPUT: q

   Simulation ends.
xxxqzzqxxx
chmod go+r *
cd ..

echo  Done.  Note that, as created, the directory demo
echo  and all files in it are publically readable.