Assignment 12, due Jul 26

On every assignment, write your name legibly as it appears on your University ID card! Homework is due on paper at the start of class on the day indicated (Tuesday or Thursday). Exceptions will be made only by advance arrangement (excepting "acts of God"). Late work must be turned in to the TA's mailbox (ask the CS receptionist in 14 MLH for help). Never push homework under someone's door!

1. Background: The Sparrowhawk instruction set is a subset of the Hawk instruction set. It contains most of the 16-bit short instructions of the Hawk, but none of the 32-bit long instructions. So, it has LIS but not LIL and it has LOADS but not LOAD. If you write USE "sparrowhawk.h" instead of USE "hawk.h" the assembler will allow you assemble code for the Sparrowhawk. If, before the USE directive, you define the symbol STRICTSPARROW, the assembler will rigidly confine you to the Sparrowhawk instruction set.

   If you leave out the definition of STRICTSPARROW, the assembler will define macros for the Hawk instructions, but these are macros. For example, if you write LEA R3,R2,LOCALVAR a macro like the following might be called:

           MACRO LEA =dst,=x,=const
             LIS  R1,const >> 8
             ORIS R1,const & #FF
             PLUS R1,x
             MOVE dst,R1
           ENDMAC
   

   The above definition ignores the possibility of PC-relative addressing and it assumes that R1 is available as a temporary for address computation.

   You can examine the entire un-simplified Sparrowhawk macros in the headers download collection on the course home page.

   a) Write similarly simplified macro for LIL. As with the code given above, ignore the possibility of external or relocatable operands. (0.5 points)

           MACRO LIL =dst,=const
             LIS  dst,const >> 16
             ORIS dst,(const >> 8) & #FF
             ORIS dst,const & #FF
           ENDMAC
   

   The above is the simplest, but of course, optimization is possible. We could detect constants that require fewer than than 24 bits and use a shorter form, with just one ORIS.

   b) Explain why the code for LEA given above uses PLUS instead of ADD. (0.5 points)

   PLUS R1,x does not change the condition codes, while ADD R1,R1,x changes the condition codes. The entire LEA macro must not change the condition codes in order to imitate the Hawk LEA instruction.

2. Background: On the Hawk, an attempt to execute an undefined instruction causes an instruction trap, transferring control to address 20₁₆. Consider installing the shortest possible trap service routine at that address:

   .       =       #20
           RTT
   

   a) Give the smallest possible Hawk main program that installs this trap handler and then tests it with an undefined instruction. (Hint: The main program contains just the undefined instruction; the total amount of assembly language involved, including the above, is under 10 lines of code.) (0.3 points)

           INT     MAIN
   MAIN:
           B       #10, #80        ; -- see appendix B.1.9 of the Hawk Manual
   .       =       #20
           RTT
   

   If we used W #8010 it would generate the same machine code. This undefined instruction has register fields that are set to zero in the above. Any nonzero value in these fields would work as well.

   There are other undefined instructions:
    B #Fx,#1x — see appendix B.1.2 of the Hawk Manual
    B #Fx,#0x — see appendix B.1.2 of the Hawk Manual
    B #00,#xx — see appendix B.1.11 of the Hawk Manual

   b) What happens when you run it? (Try single-stepping it so you can see what it does in some detail.) (0.2 points)

   It goes into an infinite loop containing just two instructions, the undefined instruction at 1000₁₆ and the RTT instruction at 20₁₆.

   It loops because the saved program counter TPC given to the trap service routine is the address of the instruction that caused the trap, so when the trap service routine returns with this value unchanged, the same instruction is executed again.

   c) Write the shortest trap handler you can that increments the trap program counter by 2, (leaving all the other registers unchanged) and then returns from trap. This trap handler converts all undefined instructions into no-ops equivalent to the built in NOP instruction. (A suggestion: Try it and see what happens.) (0.5 points)

   .       =       #20
           CPUSET  R3,TSV          ; save a register to make space to work in
           CPUGET  R3,TPC          ; use that register to hold TPC
           ADJUST  R3,PLUS2        ; increment value from TPC without CC change
           CPUSET  R3,TPC          ; put incremented value back in TPC
           CPUGET  R3,TSV          ; restore the saved register
           RTT
   

3. Background: Suppose you need to turn on the Hawk MMU. In theory, the following code should do this:

           CPUGET  R3,PSW
           SUB     R0,R3,R3
           ADJUST  R3,CMSB
           CPUSET  R3,PSW
   

   If there is an MMU included in the Hawk, this code should cause an immediate MMU trap (trap to locaiton 40₁₆), so there is obviously more to the story.

   a) What does the two instruction sequence SUB followed by ADJUST above do? A complete answer must go into enough detail to explain why it works. (0.5 points)

   The subtract instruction (equivalent to CMP R3,R3) sets the carry bit because (x – x) is the same as (x + (~x + 1)) which is the same as ((x + ~x) + 1). Note that ((x + ~x) is all ones, no matter what value x has, so adding 1 to it gives a result of zero with a carry out of the high bit.

   Another way of putting the above is that, on the Hawk, after any subtract instruction, the C condition code means not-borrow, and subtracting a number from itself never produces a borrow out of the high bit, so the carry is always 1 after such a subtraction.

   The ADJUST instruction adds the carry bit to the high bit of R3.

   The net result is to toggle the high bit of R3. If it was off, turn it on. If it was on, turn it off.

   b) What should be done before turning on the MMU in order to prevent the trap caused by the above instruction sequence. (0.5 points)

   We need to load the MMU with an entry that maps the virtual address for the current page to a page holding something sensible, for example, by mapping it to the exact same physical address.