Assignment 11, due July 29

Always, on every assignment, please write your name legibly as it appears on your University ID and on the class list! All assignments will be due at the start of class on the day indicated, and unless there is what insurance companies call "an act of God" - something outside your control; the only exceptions to this rule will be by advance arrangement.

1. Background: Consider a computer system with separate i-cache and d-cache, where the instruction fetch unit uses the i-cache to speed up instruction fetches, and the execute unit uses the d-cache to speed up load and store instructions. These caches are independent.

   The program running on this CPU transfers control to a loader (that is, a program that loads new object code into RAM from disk). The loader loads a new program into the memory formerly occupied by ther original running program, and then the loader jumps to the newly loaded code to run it. The loader itself is very small (a few tens of instructions).

   a) Assume that the i-cache is not flushed before jumping to the newly loaded program. Note what is in the i-cache at the time of this jump, and then explain the nature of the problems this could cause after the jump to the newly loaded program. (1/2 point)

   b) If the machine has a "flush cache" instruction, and if the loader executes this instruction just before the jump, how does this change your answer to part a? (1/2 point)

2. Background: The figure in chapter 13 titled "a complete system" has two caches, one split into i-cache and d-cache, between the CPU and the MMU, and the other sitting between the MMU and the main memory.

   a) Which cache or caches relate virtual addresses to the values stored there, and which relate physical addresses to the values stored there? (1/2 point)

   b) (1/2 point) Consider what happens if the contents of the MMU address translation registers are changed and no cache flush operations are done. Note what is in the different caches at the time of the MMU change, and then explain the nature of the problems this could cause after the MMU change.

   c) What cache or caches must be flushed after changing the contents of any MMU registers in order to avoid the problems mentioned in part b). (1/2 point)

3. Consider this flipflop:

   c = a nor d
   d = b nor c

   Draw the logic diagram. How do you set it? How do you reset it? How do you set the inputs to make it remember its most recent setting? Which outputs correspond to Q and Qbar? What are the most appropriate labelings of the inputs? (1/2 point)