a) Is it edge triggered (master-slave)? __Yes___________
The easy logic here is that the circuit contains 3 pairs of nor gates that are cross-connected like simple R-S flipflops. Since the circuit contains 3 flip-flop-like subcircuits, it seems natural to guess that it has behavior far more complex than a simple flipflop and might be a master-slave flipflop.
Only 1/6 of the class had difficulty reaching this conclusion.
b) Which input is the D input? ___b________________
The a input has a symmetrical effect on the c and d outputs, so it is hard to see how the value of a could be copied to, for example, c. In contrast, b has a very assymetrical impact on the output, so it is easy to imagine the value on b causing c to be set one way an d the other.
About 1/5 of the class had difficulty here.
c) Which input is the C input? ___a________________
Continuing the argument outlined above, note that if the a input is one, this forces the control inputs to the final (slave) flipflop to both be zero, allowing the slave stage to hold the value while the master stage is in a state determined by the b or data input. This is precisely the behavior we expect from the clock input to a master-slave flipflop.
About 1/5 of the class had difficulty here.
c) Which output is the Q output? ___c________________
Having concluded that b is the D input, the trick is to trace through the path from b to c and from b to d, counting the number of inverter bubbles along the path. Doing this, quickly shows that all paths through this circuit from b to d lead through odd numbers of inversion bubbles, while all paths from b to c lead through even numbers of inversion bubbles. Therefore, c must be the Q output.
This was harder, giving 1/3 of the class difficulty.
d) What input C can change the output __negative edge_____
Here, having concluded that it is a master-slave flipflop, students were expected to understand that this implied a response on either the positive or negative edge. Inferring which edge follows from the observation that a one on the a (clock) input allows the slave stage to remember. Therefore, a one-to-zero transition on the clock input must allow the strangely complex master stage to remember while allowing the data stored in the master to flow out through the stage. The conclusion that this is a negative-edge-triggered flopflop follows from this.
Only 2 got this right, while two more specified the wrong edge. All of the remainder either left it blank or gave a simple 1 or 0 as their answer instead of specifying an edge.
|_ _ _ _|_ _ _ _|_ _ _ _| |_|_|_|_|_|_|_|_|_|_|_|_| |s| exp | mantissa |
- s -- the sign bit, 1 = negative.
- exp -- the exponent, biased so that 1000 represents zero.
- mant -- a fixed point fraction, so that 100 0000 represents 0.5
when the exponent is greater than 0000, the mantissa is always normalized.
Give an algebraic expression of the form a × bc for each of the following: (0.4 points each)
a) The largest positive number in this system: 0.9919875 × 27 or approximately 1 × 27
1/4 of the class did well, 1/3 earned no credit. Among those earning partial credit, the mantissa was harder.
b) The smallest nonzero positive number: 1 × 2-15 = 2-7 × 2-8
Only a few got this right. Among those earning partial credit, the exponent and mantissa were about equaly difficult. 2/5 earned no credit.
c) The smallest normalized positive number: 1 × 2-9 = 0.5 × 2-8
None got this right. Of those earning partial credit, the exponent was harder than the mantissa. 1/2 earned no credit.
Many wrong answers on parts b) and c) involved assuming that there was a hidden bit and therefore assuming that the exponent values 0000 and 0001 both represented -7, with the hidden bit set to 1 for the latter. This assumption was not justified by the problem statement.
d) Give the binary representation of 1.0: __0_1001_1000000____
1/4 got this right. 1/4 earned no credit. Among those earning partial credit, most of the errors were in the exponent field.
e) Give the binary representation of -10.0: __1_1100_1010000____
1/9 got this right. 1/3 earned no credit. Among those earning partial credit, most of the errors were in the exponent field.
1/3 of the class gave answers to parts d) and e) based on the assumption of a hidden bit. Where this assumption was made consistently, a a single penalty of 0.4 points was assessed and the other answers were judged correct. Unfortunately, several students made the assumption of the hidden bit in some of their answers and not in others. In those cases, each answer was graded independently.
; given R3 = a floating point number
MOVE R4,R3
SR R4,11 ; now R4 = the sign bit
MOVE R5,R3
A: SR R5,7
B: TRUNC R5,5 ; now R5 = the exponent field
C: MOVE R6,R3
D: TRUNC R6,7 ; now R6 = the mantissa field
a) What does line A do? (1 point) __Shift R5 7 places right to discard the mantissa_______
1/2 gave essentially this answer. 1/2 erned partial credit by explaining the shift without saying anything to explain what it accomplishes. Only a few students earned no credit.
b) What does line B do? (1 point) __Truncate R5 keeping only 5 bits, to discard the sign__
There was an error on the exam here! Full credit was given to anyone who said either 4 bits or 5 bits, or who said that it discards the sign bit.
Almost 2/3 got full credit, while 1/6 got partial credit.
c) If you wanted this code to leave the mantissa aligned as a fixed point number with the point all the way to the left so that there are 32 bits of fraction, how would you change lines C and D? (1 point)
C: ____MOVSL___R6,R3,12_____________________________
D: ____SL______R6,13________________________________
Only 1 got this perfectly correct. 1/4 of the class had code equivalent to a move followed by a shift, with a shift count of 25. The trouble is, the shift-count field is only 4 bits, so a shift count of 25 is impossible.
1/3 of the class gave strange shift counts. Some even had shift counts of 32, which would set the destination register to zero. 1/3 of the class earned no credit.
FTIMES: ; expects R3 = plicand -- the multiplicand
; R4 = plier -- the multiplier
; returns R3 = prod -- the product
; uses R5 = plicand -- copied there
; R6 = i -- loop counter
; -- all operands are 32-bit fixed-point unsigned fractions
; with the point to the left of the leftmost bit
__MOVE____R5,R3__ ; -- set multiplicand aside
LIS R3,0 ; prod = 0;
__LIS_____R6,32__ ; i = 32
FTIMLP: ; do {
__SRU_____R4,1___ ; plier = plier >> 1
BCR FTIMEL ; if (plier's former LSB was 1) {
ADDSR R3,R5,1 ; prod = (prod + plicand) >> 1
__BR______FTIMEI_
FTIMEL: ; } else {
__SRU_____R3,1___ ; prod = (prod ) >> 1
FTIMEI: ; }
ADDSI R6,-1 ; i = i - 1
__BNE_____FTIMLP_ ; } while (i != 0)
JUMPS R1 ; return prod
A Problem: 6 instructions have been omitted from the above code. The comments are still correct. Fill in the blanks. (3 points)
Almost 2/3 of the class did perfectly on the MOVE instruction.
Almost all of the class did perfectly on the LIS instruction, although some gave LIL instructions, a change that was not penalized.
1/7 got the first SRU instruction correct. 5/7 used a plain SR instruction, for a small penalty.
3/7 got the BR instruction correctly, while 2/7 had wild answers. Partial credit went to those who branched to the wrong label or the one who used a conditional branch here.
The second SRU was harder. Only 1/12 got it correct, while 5/7 had SR instructions. Several had the wrong count or wrong register.
3/7 of the class got the final BNE correct, while 2/7 had the wrong conditional, earning partial credit. 1/7 had strange instructions.