Grade Distributions
Exam 2
Median = 3.5 X
Mean = 3.76 X
X
X X X
X X X X X
X X X X X X X
X X X X X X X X X
X X X X X X X X X X X X X
_____X_X_X_X_X_X_X_X_X_X_X_X_X_X_X_X_X_______
0 . 1 . 2 . 3 . 4 . 5 . 6 . 7 . 8 . 9 . 10
Exams 1 and 2
Median = 7.7 X
Mean = 8.27 X
X X
X X X X X
X X X X X X X X X X
X X X X X X X X X X X X X X X X
_________X___X_X___X_X_X_X_X_X_X_X___X_X___X_X_X_X_X_X_X___X_X___
0 . 1 . 2 . 3 . 4 . 5 . 6 . 7 . 8 . 9 . 10. 11. 12. 13. 14. 15
Homework 1 to 10
Median = 26.9 X
Mean = 25.97 X X
X X
X X X X X
X X X X X X
X X X X X X X X X
X X X X X X X X X X X X
_______X_X_X_____X___X_X_____X_X_____X_X_X_X___X_X_X_X_X_X_X_X___
15. 16. 17. 18. 19. 20. 21. 22. 23. 24. 25. 26. 27. 28. 29. 30
Machine Problems 1 to 4
Median = 13.1 X
Mean = 12.85 X X X
X X X X X
X X X X X X X X
X X X X X X X X X X
X X X X X X X X X X X X
___X_____X_X_X_X_X_X_X_X_X_X_X_X_X_X_X_X_X___
0 . 2 . 4 . 6 . 8 . 10. 12. 14. 16. 18. 20
Total Scores
Median = 46.9 X X
Mean = 46.86 X X
X X X X X X X
X X X X X X X X X X X X
X X X X X X X X X X X X X X X
_____X___X_X_X_X___X_X_X_X_X_X_X_X_X_X_X_X_X_X___
20. 24. 28. 32. 36. 40. 44. 48. 52. 56. 60. 64
D C B A
If this was the end of the semester, the grade scale might look something
like the above, but: We will only count the top 10 homework scores, no
matter how many are assigned, an we will only count the top 6 machine problem
scores.
Solutions and Commentary
Note that 3 groups of questions on this exam rested on interpreting bus traps.
The code fragments and Hawk emulator displays used for these questions were
anonymized but based on actual student submissions for machine problems. Any
student who regularly attempted to solve the machine problems shouldwhave
encountered many of these error conditions and found their interpretation to
be routine.
HAWK EMULATOR
/------------------CPU------------------\ /----MEMORY----\
PC: 00000000 R8: 00000000 FFFFFC: --
PSW: 00007F00 R1: 00000000 R9: 00000000 FFFFFE: --
NZVC: 0 0 0 0 R2: 00010068 RA: 00000000 ->000000: LIL R2,#010064
R3: 00001094 RB: 00000000 000004: JSR R1,#00021C
R4: 00000004 RC: 00000000 000008: LIS R1,#00
R5: 00000050 RD: 00000000 00000A: LIL R0,#001000
R6: 00000000 RE: 00000000 00000E: NOP
R7: FF000000 RF: 00000000 000010: CPUSET R2,#3
**HALTED** r(run) s(step) q(quit) ?(help)
Bus Trap. Trap PC = #0000100C
Trap MA = #00000004
13 ; Main program activation record
14 ;RETAD = 0
15 HEAD = 4
16 ARSIZE = 8
17
18 MAIN:
+00000000: F1 A2 19 STORES R1,R2
+00000002: 12 C0 20 ADDSI R2,ARSIZE
+00000004: E3 +000000 21 LIL R3,MP5DATA
+00000008: E4 000004 22 LIL R4,HEAD
+0000000C: F0 A4 23 STORES R0,R4 ; head = null
- Give the line number of the instruction that directly caused the trap.
___23_________
25 got this right. Most wrong answers referred to lines 21 or 22.
Line 21 is entirely correct. Line 22 was indeed the root cause of the trap,
but that was not what the question asked about.
This should have been trivial because it does not involve understanding the
code at all. The trap PC in the bus-trap error message
tells you it's address 0000100C16, which is (after taking relocation
into account) address 0000000C16 in the listing, or line 23.
- Did a register hold an bad value leading to this trap? If so, which?
______R4_________
30 got this right. No register, R2 and R3 were equally
popular wrong answers. Looking at the Hawk emulator display, it is easy
to see that R2 is a legal RAM address, and R3 is a legal
ROM address, and no instruction that references these instructions does so
in a way that would cause a trap.
- Give the line number of the instruction you should change to fix this.
___22_________
30 got this right. Lines 20, 21 and 23 were popular wrong answers. Nothing is
wrong with these. Line 23 caused the trap, but it does exactly
what the comment describes, so long as R4 holds the right value.
Line 22, loading the wrong value into R4. The symbol HEAD
is defined on line 15 as the index of a field of the activation record, and
the code for line 22 is not treating it as such.
- Give the correct instruction for that line
___________LEA______R4,R2,HEAD__________
1 got this right. At least 8 more suggested a LOAD instruction
instead of LEA. They were on the right track, but line 23 needed
the address of the local variable, not its value.
- The basic mistake was
addressing a ___LOCAL___ variable as if it was ___GLOBAL___
20 got this right. The code of lines 22 and 23 were exactly correct had
HEAD been the name of a statically allocated (by COMMON)
global variable.
- An indented line in a Makefile is a
_________SHELL_COMMAND_____________________
used to make the target immediately above it.
20 got this right. 8 left it blank, 5 each said "pointer" or "file list."
Most of the wrong answers attracted 2 or fewer.
"File list," "target" and "source" have something to do with Makefiles, but
most wrong answers were totally off the wall, as if someone was playing
buzzword bingo without regard to meaning.
HAWK EMULATOR
/------------------CPU------------------\ /----MEMORY----\
PC: 00000000 R8: 00000000 FFFFFC: --
PSW: 00007F00 R1: 0000104E R9: 021430F1 FFFFFE: --
NZVC: 0 0 0 0 R2: 0001006C RA: 00000000 ->000000: LIL R2,#010064
R3: 0001FFF0 RB: 00000000 000004: JSR R1,#00021C
R4: 00000000 RC: 00000000 000008: LIS R1,#00
R5: 021430F1 RD: 00001088 00000A: LIL R0,#001000
R6: 0001046C RE: 00000000 00000E: NOP
R7: 0001FFEC RF: 00000000 000010: CPUSET R2,#3
**HALTED** r(run) s(step) q(quit) ?(help)
Bus Trap. Trap PC = #00001072
Trap MA = #021430F0
+00000066: F5 54 0004 98 LOAD R5,R4,NXT
+0000006A: F0 E5 99 TESTR R5
+0000006C: 0A 04 100 BZR NOTNEXT ; if (p->nxt==null) {
+0000006E: F9 54 0004 101 LOAD R9,R4,NXT
+00000072: F3 A9 102 STORES R3,R9 ; p->nxt = new
+00000074: F0 B1 103 JUMPS R1 ; return
104 NOTNEXT: ; }
+00000076: F4 F5 105 MOVE R4,R5 ; p = p->nxt
+00000078: 00 FA 106 BR INSLOOP ; }
- Give the line number of the instruction that directly caused the trap.
_____102______
30 got this right. The most popular wrong answer, given by 8, was line 98.
Lines 99, 100, 101 and 103 were suggested by 3 for 4 each. None of these
was involved with the trap documented by the Emulator display quoted above.
As with problem 1, this should have been trivial because it does not involve
understanding the code at all, just the bus-trap error message and assembly
listing formats. Note that both lines 98 and 102 produce wrong results
because of a bad value in R4, but that value was not the cause of
this trap.
- Did a register hold an bad value leading to this trap? If so, which?
________R9_______
23 got this right. 9 said no register was involved, while 11 said R5.
The emulator display quoted above shows that R5 and R9 both
contain the nonsense memory address 021430F1, the same as the trap MA
given in the error message. Identifying the correct instruction is essential
to figuring out which register was the cause.
- Give the line number of the instruction you should change to fix this.
_____101______
25 got this right. 6 suggested changing line 102 (with useless suggested
changes) and 7 suggested changing line 98 (which needs no changes).
- Give the correct instruction for that line
______LEA_____R9,R4,NXT_________________
4 got this right. 4 more proposed an alternative solution, deleting line
101 and changing line 102 to STORE R3,R4,NXT.
Making the above repair does not fix the program. There will still be a bus
trap because the value of R4 is wrong, but it brings the code in
the quoted part of the listing into conformance with the comments on that code.
The cause of the problem value in R4 must be outside this code snippet.
- The basic mistake was
loading variable's ___VALUE___ instead of its ___ADDRESS___
15 got this right. Another 20 earned partial credit by exchanging "value"
and "address." Many lost some credit by using the word "pointer" instead of
"address." The problem is, the word "pointer" is a bit ambiguous, since people
use the word pointer to refer both to variables that hold addresses and to
the address held in such a variable.
- When c = 0, what is x as a function of a and b?
x = _______a_+_b___(or)_____________
15 got this right, and 4 more gave long expressions that can be algebraically
simplified to or for a penalty. 15 gave either 0 or 1, suggesting wild
guesses. 6 each gave nand and xor. Frameworks for truth tables
were provided in the scratch space, but few students made effective use of
these.
It is possible to get an intuitive sense of how this circuit works. If the
c input is false, the leftmost nand gate has a constant 1 output.
That constant 1 makes each of the middle and gates behave as inverters.
Applying De Morgan's law then converts the right-most nand (with its
inverted inputs) to an or.
- When c = 1, what is x as a function of a and b?
x = _______a_⊕_b___(xor)____________
15 got this right, and 2 more gave long expressions that can be algebraically
simplified to xor for a penalty. The wild guesses were very similar to
those given for question 12.
It is possible to get an intuitive sense of how this circuit works. If either
a or b is zero, the reasoning given for problem 12 applies,
so the circuit behaves like an or gage. When a and b
are both 1, however, the left nand gate output goes to zero, forcing
x to zero. That is, the output is 1 if either
a and b is 1, but not both. That is, xor.
HAWK EMULATOR
/------------------CPU------------------\ /----MEMORY----\
PC: 00000000 R8: 0000109C FFFFFC: --
PSW: 00007F04 R1: 00001024 R9: 00000000 FFFFFE: --
NZVC: 0 1 0 0 R2: 00010064 RA: 00000000 ->000000: LIL R2,#010060
R3: 00000000 RB: 00000000 000004: JSR R1,#00021C
R4: 0000109C RC: 00000000 000008: LIS R1,#00
R5: 00000000 RD: 00000000 00000A: LIL R0,#001000
R6: 00001014 RE: 00000000 00000E: NOP
R7: 000010A3 RF: 00000000 000010: CPUSET R2,#3
**HALTED** r(run) s(step) q(quit) ?(help)
Bus Trap. Trap PC = #00001044
Trap MA = #00000000
50 ; Activation record for ADDSORT
51 ;RETAD = 0
52 ARR = 4 ; pointer to array
53 ASIZE = 8 ; size of array
54 VALUE = 12 ; value to add
56 ARSIZE = R10
57
58 ADDSORT:
+00000044: F2 A3 59 STORES R2,R3
+00000046: F3 22 000C 60 STORE R3,R2,VALUE
+0000004A: F2 53 0004 61 LOAD R2,R3,ARR ; -- base of array
+0000004E: F4 53 0008 62 LOAD R4,R3,ASIZE
+00000052: F4 64 0001 63 ADDI R4,R4,1
+00000056: F4 23 0008 64 STORE R4,R3,ASIZE ; asize = asize + 1
- Give the line number of the instruction that directly caused the trap.
___59_________
20 got this right. 6 suggested line 64, which has a big problem that did
not cause this trap. 4 or 5 suggested lines 60, 61, and 62, all of which
have problems that did not cause this trap.
5 suggested line 56, which is a but, but not an executable instruction and
therefore not capable of causing a trap. They got a little credit simply
for recognizing nonsense in the code.
As with problem 1, this should have been trivial because it does not involve
understanding the code at all, just the error message and listing.
- Did a register hold an bad value leading to this trap? If so, which?
_____R3_(none)__
30 got this right. 15 said R2, a register that, at the time of this
trap, had the perfectly sensible value 00010064. It is true that,
after line 61 is executed, that value will be corrupted, but the error in that
line did not cause this trap.
R3 was acceptable because its value did cause the trap, but
saying "none" was also OK because the error was using R3 when
R2 should have been used. The actual value in R3 was
largely irrelevant.
- Give the line number of the instruction you should change to fix this.
___59_________
20 got this right. 5 each suggested 60, 61 or 62. Line 60 is entirely correct,
Lines 61 and 62 contain errors, but they are not related to this trap.
10 suggested line 56. The error on that line did not cause this trap, but
they got a little credit if they fixed it correctly.
- Give the correct instruction for that line
_____________STORES___R1,R2_____________
11 got this right. 10 more got partial credit for fixing line 56 correctly.
- Whoever wrote this didn't understand
_______________ACTIVATION_RECORDS______
10 got this right and 8 ore earned partial credit for clearly understanding
that the code manages to mangle its return address. The other errors
in this code all seem related to serious problems with activation record
management.
TBIT R4,0
BBR BIT0
SL R3,1
BIT0:
TBIT R4,1
BBR BIT1
SL R3,2
BIT1:
TBIT R4,2
BBR BIT2
SL R3,4
BIT2:
TBIT R4,3
BBR BIT3
SL R3,8
BIT3:
TBIT R4,4
BBR BIT4
SL R3,16
BIT4:
|
ADDSL R3,R3,5
ADDSL R3,R3,3
- The above instruction sequence computes R3 = ___R3_×_297___
17 got this right. It is very hard to find a pattern in the wrong answers,
which offered multipliers ranging from 0 to 1024. The only wrong answer
that was noticably more popular than the others was 8.
The first ADDSL multiplies by 33,
the second by 9 and 33 × 9 = 297.
- Assuming that R4 < 32, the instruction sequence to the left
computes
R3 =
________R3_<<_R4_______________________
Only 2 got this right. Another 3 earned partial credit for variations on
R3 2R4, each missing a different part of
the expression. Wrong answers were as varied as for problem 19. The only
one given by more than one student was R3 << 8.