Assignment 12, due Dec 5

Solutions

Part of the homework for CS:2630, Fall 2019
by Douglas W. Jones
THE UNIVERSITY OF IOWA Department of Computer Science

Recall that a trap handler has the following outline, given in more detail in Section 13.3 of the Hawk manual (but with one error):
1. Save CPU state
2. Handle trap (the error is in this part)
3. Restore CPU state and return from trap
This question deals with the middle segment, step 2 above.
a) Suppose we wanted a trap handler to convert all undefined Hawk instructions to short (16-bit) no-op instructions. Give the shortest possible code to replace the code given in the hawk manual for step 2. (0.5 points)
```
        LOAD    R3,R2,svPC
        ADDSI	R3,2
        STORE   R3,R2,svPC      ; svPC = svPC + 2
```
Explanation: At the time of the trap, the saved PC points to the undefined instruction that caused the trap. All that is needed to make that instruction into a 16-bit no-op is to return from trap with the PC incremented by 2.
b) Give the smallest possible code that you could add to part a) above that makes all of the unimplemented instructions set the condition codes to the unlikely value 1100 (both negative and zero at the same time) before returning, while making no other changes to the PSW. (0.5 points)
```
        LOAD    R3,R2,svPSW
        SR      R3,4            ; -- first set condition codes to 0000
        SL      R3,4            ; svPSW = svPSW & 0xFFFFFFF0
        ADDI    R3,R3,2#1100    ; svPSW = svPSW | 0xC -- now CC = 1100
        STORE   R3,R2,svPSW
```
There are, of course, many other solutions. Consider this one:
```
        LOAD    R3,R2,svPSW
        LIS     R4,2#1111       ; -- first set condition codes to 1111
        OR 	R3,R4           ; svPSW = svPSW | 0xF
        ADDSI   R3,-2#0011      ; svPSW = svPSW - 0x3 -- now CC = 1100
        STORE   R3,R2,svPSW
```
Regardless of which version is used, this code would go immediately after the code given in part a).
c) Find and correct the error in the code given in Section 13.3 of the Hawk manual. (0.5 points)
```
The JSRS R1,R3 should be JSRS R1,R1.
```
Background: Look at the TLB entry format used by the Hawk, as documented toward the end of Chapter 14 of the Course Notes or in Section 1.3.5 of the Hawk Manual.
a) Why is it necessary that it be possible to turn off cacheing for some particular page of memory? (Hint: The reason is related to exercise c in Chapter 14.) (0.5 points)

We need to turn off cacheing for pages that map to input-output device registers so that changes in device register status bits will be visible to programs.
If the cache was not turned off, the cache would capture the value of the status register on the first iteration of a polling loop and then all future iterations would see the cached value. Any change in the actual status register would remain invisible, and therefore, the program would be stuck in the polling loop.

b) For what range of addresses in the Hawk memory address space is it particularly likely that cacheing will be turned off? (Hint: This is a global question that integrates information from a wide range of different parts of this course.) (0.5 points)

The input output device registers are supposed to be at physical addresses at or above FF000000₁₆.
A problem: Look at the Hawk virtual address format. Suppose that each page table entry contained a 27-bit physical page number plus and the 5 flags (CRWXV) used in each HAWK TLB entry. How many bytes, total, will be occupied by the entire page table. (0.5 points)

There are 20 bits in the page number field of a Hawk address, so the page table must have 2²⁰ entries. How many bytes per entry? 27 bits plus 5 flags makes 32 bits or 4 bytes, which is one word, so the page table will occupy 2²⁰ words, which is 2²² bytes, which is about 4 million bytes.