_ _ _ _ s = sign of mantissa, 1 bit, 0 = positive
|_|_|_|_| exp = exponent, biased, 2 bits
|s|exp|m| exp = 11 - not a number or infinity if m=0
exp = 01 - represents the value zero
exp = 00 - mantissa not normalized
m = mantissa, hidden bit in 1's place.
hidden bit = 1 for normalized numbers
Convert each of the following binary floating point numbers to decimal, either in the form 5.6 or infinity or nan, as the case may be. (1.6 points)
a) 0 0 0 0 e) 0 1 0 0 i) 1 0 0 0 m) 1 1 0 0 ______+0.0__ ______+2.0__ ______-0.0__ ______-2.0__ b) 0 0 0 1 f) 0 1 0 1 j) 1 0 0 1 n) 1 1 0 1 ______+0.5__ ______+3.0__ ______-0.5__ ______-3.0__ c) 0 0 1 0 g) 0 1 1 0 k) 1 0 1 0 o) 1 1 1 0 ______+1.0__ ______+inf__ ______-1.0__ ______-inf__ d) 0 0 1 1 h) 0 1 1 1 l) 1 0 1 1 p) 1 1 1 1 ______+1.5__ ______+NaN__ ______-1.5__ ______-NaN__
1/3 of the class did perfectly.
2/5 gave wrong answers for parts f and n, typically giving 2.5; apparently, the sequence 0.5, 1.0, 1.5, 2.0, 2.5 is very attractive.
1/3 gave wrong answers for parts b and j, typically giving 0.25, indicating that they did not understand that the exponent values 00 and 01 signified the same exponent value, 0.
1/4 had difficulty with parts e and m. The difficulties here are hard to classify.
2/9 gave wrong answers for parts h, p and o; encoding of not-a-number values is not intuitive, nor is the concept of negative infinity. In contrast, only 1/8 had trouble with part g, positive infinity.
MOVE R1,R3
ADDSL R3,R1,2
ADDSL R3,R1,3
ADDSL R3,R3,1
A problem:
What transformation does it perform? (1 point)
R3 = __R3×123______________
2/5 got this right. 1/4 gave the answer R3×135; this was the result of misreading the second ADDSL instruction as ADDSL R3,R3,3. Of the remaining students, no more than two students gave any particular answer, most of which involved clerical errors in interpreting the two popular answers.
The following multipliers were given by one (or occasionally two) students each: 17, 28, 42, 44, 64, 96, 105, 115, 132, 164, 174, 1200.
MACRO LOADUCC =r,=x,=f ; the u stands for un-aligned
IF f & #3 = 0
LOADCC r,x,f
ELSEIF f & #3 = 1
LOAD R1,x,f
SRU R1,8
LOAD r,x,f+4
SL r,12 ; ***
ADDSL r,R1,12 ; ***
ELSEIF f & #3 = 2
__LOAD___R1,x,f___
__SRU____R1,16____
__LOAD___r,x,f+4__
__ADDSL__r,R1,16__
ELSE ;F & #3 = 3
__LOAD___R1,x,f___
__SRU____R1,12____
__SRU____R1,R2____
__LOAD___r,x,f+4__
__ADDSL__r,R1,8___
ENDIF
ENDMAC
a) On the lines marked with ***, why can't we replace them with ADDSL r,R1,24? (0.5 points)
__The maximum count for shift instructions is 16___________ ___________________________________________________________
1/3 got this right. Wrong answers were difficult to categorize, but it is clear that a significant number of students thought that large shift counts such as 24 were perfectly acceptible in the 4-bit shift-count field.
b) Fill in the blanks for the code for the ELSEIF clause above. (1.2 points)
c) Fill in the blanks for the code for the ELSE clause above. (1.5 points)
For the final two parts, only a few students did well, most students replicated the set of instrucitons from the first elseif clause and then attempted to infer the pattern to use in modifying the shift counts without really understanding the code they were modifying. As a result, over 2/3 used the wrong shift count on the SRU in part b and added an extra SL in parts b and c, and 5/9 made wild changes to the displacement on the LOAD instructions. Essentially all of these students also failed to understand part a, and therefore did not use an extra shift instruction when shift counts greater than 16 were required or did not eliminate extra shifts when counts under 16 were involved.
Note that the format of the LOADUCC macro should have been familiar to essentially everyone since it was based on the kind of macros that students had to deal with in Machine Problem 5.
Note: In both parts b and c, extra blanks have been provided to allow for inefficient code.
|
|
q = q nand x
q = q nand a
x = b nand not a
a) Draw the circuit in the space to the right. (1 point)
2/5 did perfect work here, almost all giving a diagram comparable to the top one at the right (although usually a bit messy). The most common wrong answers involved reproducing some kind of flipflop diagram from the notes, usually with more nand gates than suggested by the given equations.
The second diagram to the right is equivalent. Nobody gave this one, but it should help make it clear that this flipflop design is based on a 2 to 1 multiplexer, where a is the control input, b is the data input selected when the a is low, and q is the data input selected when a is high.
b) Which is the data input? ___b________ (0.5 point)
Over 1/3 got this right. under 1/3 answered a. The remainder gave answers that were difficult to classify, despite the fact that there were really only two reasonable answers, a and b.
Several of those that said a was the data input had drawings that strongly suggested their reasoning. Typically, this involved noting that, in the classical type D latch, the data input is inverted on the way to q while it is not inverted on the way to q. The a input follows this logic, but this is misleading.
c) Is this edge triggered? ___no_______ (0.5 point)
Over 1/3 got this right. under 1/3 said yes. Again, the remainder gave answers that were difficult to classify despite the fact that this was a yes no question.
The answer was fairly obvious, simply based on the complexity of the flipflop. Master-slave and edge-triggered flipflops all have considerably more logic involving a minimum of two feedback loops and sometimes more, in fully developed edge-triggered designs. The flipflop given had only one feedback loop, so it can't be edge triggered.
d)
What clock value or change
makes it act on its input? __a=0_______
(0.5 point)
1/4 got this right. Partial credit was given for those who concluded that it was an edge triggered flipflop that changed its output on the falling edge (1/5) or when a=0 (1/10).
It was difficult to give credit to those who had part b wrong, because treating input b as the clock input
; here: R3 = points to savearea->pc ; R4 = pc -- user's ; R5 = M[pc] -- fullword ; R6 = ir = M[pc] -- halfword ; R8 = dst field of IR (bits 3 to 0) MOVE R7,R6 SR R7,8 ; acc = ir bits 8-15 -- const part 1 ADDSI R4,2 ; pc = pc + 2 LOADS R5,R4 EXTH R6,R5,R4 ; ir = M[pc] -- const part 2 ADDSI R4,2 ; pc = pc + 2 SL R6,16 ; *** SR R6,8 ; *** OR R7,R6 ; acc = acc | sxt(ir << 8) ADDSL R8,R3,2 ; -- compute address of saved r[dst] STORES R7,R8 ; r[dst] = acc STORES R4,R3 ; -- save updated pc to finish job
a) Why not replace the two lines marked with *** with one line reading SL R6,8? (0.3 points)
_____this code sign extends R6_________________________________
_____the alternative SL does not_______________________________
Nobody got this right, but 1/5 mentioned truncation (the opposite of sign extension) for partial credit, and 1/10 specifically said the added complexity is used to avoid truncation, earning better partial credit.
b) The ADDSL instruction above has a shift count of 2, and it seems to be computing the memory address of r[dst]. In this context, why a shift count of 2? (Hint: Why not a shift count of 1 or 3?) (0.4 points)
_____dst selects a 4-byte word in the array R__________________
_____the shift count of 2 multiplies by 4______________________
1/9 got this right, 1/7 earned partial credit by talking about alignment.