Assignment 12, due Dec 5

Solutions

Part of the homework for CS:2630 (22C:60), Fall 2014
by Douglas W. Jones
THE UNIVERSITY OF IOWA Department of Computer Science

Background: To solve Machine Problem 6, you will have to figure out how to make the virtualized LEACC and LOADCC instructions set the condition codes. The return-from-trap code starting at the label INSTDONE in mp6.a restores the condition codes from the PSWSV field of the trap-save area.
Note: Your answers below should all take into account the fact that they are running inside a trap service routine on a Sparrowhawk processor, so of course, you may not use any 32-bit Hawk instructions.
a) Assuming you have just used an ADD to compute the effective address in the process of virtualizing an LEACC instruction, give code to load the resulting condition codes into R10. Hint: Review Sections 1.3.4 and 11.5 of the Hawk Manual. (0.4 points).
```
        CPUGET  R10,PSW
```
b) Assuming that R11 and up are available, and that R3 points to the PCSV field of the register save area, write code to save the conditon codes from R10 to the PSWSV field of the trap-save area. (0.6 points).
First, here is some very conservative code that works "in ignorance", not paying any attention to the context. The PSW contains a number of fields, and this code avoids changing any of the fields it doesn't understand:
```
        LIS     R11,PSWSV-PCSV
        SUM     R11,R3          ; -- R3 points to PSWSV
        LOADS   R12,R11         ; -- get the saved PSW
        STUFFH  R11,R10,R0      ; -- put the condition codes into the PSW
        STORES  R12,R11         ; -- update the stored PSW
```
In fact, we don't need this complicated code, but to discover this, you need to read the entire trap service routine from the point it first sets the stores the processor status word in PSWSV to the point where your code does its CPUGET instruction to get the updated condition codes. The key thing to note is that no instructions in this entire range modify the level or prior fields of the PSW, so you can get away with this simplified code:
```
        LIS     R11,PSWSV-PCSV
        SUM     R11,R3          ; -- R3 points to PSWSV
        STORES  R12,R11         ; -- update the stored PSW
```
Many students will give the above answer without noting the complexity of the logic needed to justify it.
What about the BCD carry field of the PSW? LEACC changes this, so you've got to update it, but since we've hardely mentioned this field, no penalty will be assessed for people who get this wrong. You'd never notice this field unless you were using ADJUST instructions with the BCD or EX3 options, and even then, you might never notice if the virtualization got the adjustment wrong because most use of ADJUST will be right after ADD instructions, with no invervening 32-bit instructions.
Background: Suppose your machine has a CPU able to execute 1 instruction every nanosecond, and it has a simple write-through cache with a 1024 word capacity, while the main memory has a 50 nanosecond cycle time.
For this problem, ignore load and store operations and focus solely on memory cycles supporting instruction fetches.
a) On the hawk, roughly what fraction of instruction fetches involve memory cycles? (0.3 points)

Instructions are mostly 16 bits, words are 32 bits, so we'd expect half of the instructions fetches to involve memory cycles for the fetch.

b) How fast would this machine be, in instructions per time, if there was no cache? (0.3 points)

If there was no overlap of fetch and execute, we would fetch one word (spending 50 nanoseconds) and then execute 2 instructions (spending 2 nanoseconds), so our instruction execution rate would be one instruction every 26 nanoseconds, on average.
If there was overlap of fetch and execute, we would exeucte one instruction every 25 nanoseconds, on average.

c) What fraction of memory cycles would have to involve cache hits for the CPU to achieve an average execution rate of 1 instruction every 2 nanoseconds? (0.4 points)

We would need a cache hit rate of about 25 to 1, that is, 25 hits per cache miss.
Background: If your Sparrowhawk machine doesn't have an MMU and you are writing a trap handler to virtualize the full Hawk instruction set, you can write code like this to load the next halfword of the instruction stream into a register:
```
	PLUS    R3,R2		; -- point to user's pc
	LOADS   R4,R3		; -- get user's pc
	LOADS   R5,R4		; -- fetch instruction word ***
	EXTH    R6,R5,R4	; ir = M[tpc]
```
(The above code is lifted from mp6.a)
a) Exactly one of the instructions quoted above would not necessarily produce the correct result if the Sparrowhawk had an MMU attached to it. Which one? (0.3 points)

If the user code was running with the MMU turned on and the trap service was running with the MMU turned off (the normal state of affairs), then the the fetch of the instruction word (LOADS R5,R4 starred above) might not fetch the correct instruction word.

b) Why is it possible that it could produce the correct result? Hint: Review Section 1.3.5 of the Hawk Manual. The answer is quite short and not highly technical. (0.3 points)

If the user code was running with the MMU off (possible if parts of the operating system are written in Hawk code instead of Sparrowhawk code) or if, by random chance, the MMU happenes to map some range of virtual addresses to the exact same physical addresses.

c) What would the trap handler need to do in order to guarantee that it always produced the right result — do not write code, write a brief English description of what it would have to do, not how it would do it. (0.4 points)

The trap handler would have to translate the user's virtual address to the corresponding physical address "by hand", accessing the page table (or other information from the MMU) in order to use the corresponding physical address.