Assignment 12, due Dec 5

On every assignment, write your name legibly as it appears on your University ID card! Homework is due on paper Homework is due on paper at the start of class on the day indicated (usually Friday). Late work must be turned in to the TA's mailbox (ask the CS receptionist in 14 MLH for help). Never push homework under someone's door!

1. Background: To solve Machine Problem 6, you will have to figure out how to make the virtualized LEACC and LOADCC instructions set the condition codes. The return-from-trap code starting at the label INSTDONE in mp6.a restores the condition codes from the PSWSV field of the trap-save area.

   Note: Your answers below should all take into account the fact that they are running inside a trap service routine on a Sparrowhawk processor, so of course, you may not use any 32-bit Hawk instructions.

   a) Assuming you have just used an ADD to compute the effective address in the process of virtualizing an LEACC instruction, give code to load the resulting condition codes into R10. Hint: Review Sections 1.3.4 and 11.5 of the Hawk Manual. (0.4 points).

   b) Assuming that R11 and up are available, and that R3 points to the PCSV field of the register save area, write code to save the conditon codes from R10 to the PSWSV field of the trap-save area. (0.6 points).

2. Background: Suppose your machine has a CPU able to execute 1 instruction every nanosecond, and it has a simple write-through cache with a 1024 word capacity, while the main memory has a 50 nanosecond cycle time.

   For this problem, ignore load and store operations and focus solely on memory cycles supporting instruction fetches.

   a) On the hawk, roughly what fraction of instruction fetches involve memory cycles? (0.3 points)

   b) How fast would this machine be, in instructions per time, if there was no cache? (0.3 points)

   c) What fraction of memory cycles would have to involve cache hits for the CPU to achieve an average execution rate of 1 instruction every 2 nanoseconds? (0.4 points)

3. Background: If your Sparrowhawk machine doesn't have an MMU and you are writing a trap handler to virtualize the full Hawk instruction set, you can write code like this to load the next halfword of the instruction stream into a register:

   	PLUS    R3,R2		; -- point to user's pc
   	LOADS   R4,R3		; -- get user's pc
   	LOADS   R5,R4		; -- fetch instruction word
   	EXTH    R6,R5,R4	; ir = M[tpc]
   

   (The above code is lifted from mp6.a)

   a) Exactly one of the instructions quoted above would not necessarily produce the correct result if the Sparrowhawk had an MMU attached to it. Which one? (0.3 points)

   b) Why is it possible that it could produce the correct result? Hint: Review Section 1.3.5 of the Hawk Manual. The answer is quite short and not highly technical. (0.3 points)

   c) What would the trap handler need to do in order to guarantee that it always produced the right result — do not write code, write a brief English description of what it would have to do, not how it would do it. (0.4 points)