Assignment 11, due Nov 14

Solutions

Part of the homework for CS:2630 (22C:60), Fall 2014
by Douglas W. Jones
THE UNIVERSITY OF IOWA Department of Computer Science

  1. Background: The preliminary code for mp5.h distributed with the assignment mp5.h would assemble 
            LEACC   R3,X

    as 

            qPCRELq = X-(.+6)
        LIS     R1,qPCRELq >> 8
        ORIS    R1,qPCRELq & #FF
        PLUS    R1,R0
        MOVECC  R3,R1

    Here, we are asking about things you might have tried in solving MP5 that do not work.

    a) Why can't we replace PLUS R1,R0 / MOVECC R3,R1 with ADD R3,R1,R0? (Hint: Find out why the ADD instruction produces a completely different result.) TESTR and CMPI? (0.3 points).

    In PLUS R1,R0, Section 11.3 of the Hawk manual says that R0 in the src field refers to the program counter.

    In ADD R3,R1,R0, Section 8.2 of the Hawk manual says that R0 is not permitted in the s2 field, while later text says that it means the constant zero.

    Clearly, neither interpretation of R0 in the context of the ADD R3,R1,R0 means the same thing as it means for PLUS R1,R0.

    In its shortest form, one could say that the problem is the non-uniform way that the Hawk treats R0.

    b) It would be nice to shorten the LIS / ORIS instruction to just an LIS if the value of qPCRELq is between -128 and +127, but this produces big problems when you try to do it. Why? (Hint: The answer has more do with the assembler than with the Sparrowhawk.) (0.4 points).

    The SMAL assembler uses two passes to resolve forward references. If we try to write something like this:

     IF ((x-.)>-128)&((x-.)<127)

    it will not work because, during pass 1, forward references (where the value of x is unknown) will lead to undefined expressions, so the macro may assemble differently during pass 1 and pass 2, leading to all label definitions after the point of the macro call being flagged as having different values in pass 1 and pass 2.

    Despite the variety of functions defined in section 2.6 of the SMAL manual that allow testing of whether symbols are defined yet or are forward references, none of them suffice to solve this problem.

    A short answer referring to two pass assembly and problems with multiple label definition should earn partial credit.

  2. Background: Consider this logic diagram, a slightly modified version of the master-slave flipflop diagram from the middle of chapter 12 of the notes:

    schematic diagram of a D flipflop

    Two new inputs have been added to this flipflop, labeled X and Y.

    a) How must the X and Y inputs be set so that this flipflop will behave exactly like the flipflop in the notes? (0.3 points)

    If you add an extra input to an and or a nand gate and hold the value of that input at 1, you can ignore that input. In algebraic terms:

    a and b and true = a and b

    Therefore, if we hold X and Y equal to 1 (which is true), the flipflop will behave exactly like the one in the notes.

    b) Given that C is held constant at zero or one and X and Y are initially at the values you proposed for part a, what happens to the outputs if there is a pulse of the opposite value on the X input. (0.4 points)

    Given the answer to part a above, we are talking about a negative (false or zero) pulse on X. While X is low, the Q outputs of both the master and slave flipflops are forced high (true or one).

    If the clock is 1, the slave (output) flipflop is ignoring the D input so this pulse on X sets the slave flipflop and therefore determines the output of the entire master-slave flipflop.

    If the clock is 0, the master (input) flipflop is ignoring the D input while the slave passes on the master value, so this pulse on X sets the master which determines the output of the entire master-slave flipflop.

    In summary, a negative pulse on X sets the master-slave flipflop.

    There was no need here to ask about Y because the flipflop is symmetrical and a very similar argument can be made there, leading to the conclusion that Y is the reset input.

  3. Background: Look at the code for the Hawk monitor. As written, when a trap occurs, for example, a bus trap, the monitor saves the registers, outputs an error message (Bus Trap.) and the value of the saved PC and Trap Memory Address, and finally, restores the registers and then does a return from trap to location 0 in memory. Setting the PC to zero halts the Hawk emulator. The result is that, when the emulator halts, all of the registers it shows hold the values they had at the tim of the instruction that caused the trap, except the PC (which is zero).

    a) It didn't really save and restore all the registers from R1 to R15. Which registers did the code actually save and restore? (0.3 points)

    It only saves and restores registers 1 through 7.

    b) Why didn't the monitor's trap service routine need to save the other registers? (0.5 points)

    None of the code between the save and restore needed to use registers 8 to 15, so they retain their value.

  4. Background: Look at the code for the Hawk monitor and consider making changes so that the bus trap handler could raise a software exception. Obviously, the monitor would need to declare the exception, for example, following the outline at the start of chapter 13 of the notes, it could start with this: 
    	COMMON  BUSTRAP, EXSIZE

    The monitor would install a default exception handler for a bus trap exception before launching the user program. The default handler would output the exact same error message the monitor currently outputs, and then it would halt, exactly as the current monitor does. As a consequence of this change, users could install their own handler for this (and other) trap conditions.

    There are two ways a trap handler in the monitor could transfer control to the handler:

    1. It could immediately load R2 with the EXAR field of the common, and then jump to the address in the EXHAND field of the common, or

    2. After saving the registers, it could copy the EXAR and EXHAND fields of the common into the save location for R2 and PC and then restore the registers from the save area and return from trap.

    a) Which would lead to faster trap handling? (0.3 points)

    Option 1 is faster. The word "immediately" is a pretty good hint here!

    b) Is one of these solutions incorrect in any formal sense of the word? Why? You may need to read ahead in the notes to determine this. (0.5 points)

    Option 1 is incorrect. The problem is, you cannot write a handler that behaves "exactly as the current handler" by following option 1. Option 1, as given, does not mention saving and restoring registers, so there is no way for the default handler to halt with the processor status word and registers 1 to 15 set to the values they had at the time of the trap.