Assignment 11, due Nov 14

On every assignment, write your name legibly as it appears on your University ID card! Homework is due on paper Homework is due on paper at the start of class on the day indicated (usually Friday). Late work must be turned in to the TA's mailbox (ask the CS receptionist in 14 MLH for help). Never push homework under someone's door!

1. Background: The preliminary code for mp5.h distributed with the assignment mp5.h would assemble

           LEACC   R3,X
   

   as

           qPCRELq = X-(.+6)
           LIS     R1,qPCRELq >> 8
           ORIS    R1,qPCRELq & #FF
           PLUS    R1,R0
           MOVECC  R3,R1
   

   Here, we are asking about things you might have tried in solving MP5 that do not work.

   a) Why can't we replace PLUS R1,R0 / MOVECC R3,R1 with ADD R3,R1,R0? (Hint: Find out why the ADD instruction produces a completely different result.) (0.3 points).

   b) It would be nice to shorten the LIS / ORIS instruction to just an LIS if the value of qPCRELq is between -128 and +127, but this produces big problems when you try to do it. Why? (Hint: The answer has more do with the assembler than with the Sparrowhawk.) (0.4 points).

2. Background: Consider this logic diagram, a slightly modified version of the master-slave flipflop diagram from the middle of chapter 12 of the notes:

   Two new inputs have been added to this flipflop, labeled X and Y.

   a) How must the X and Y inputs be set so that this flipflop will behave exactly like the flipflop in the notes? (0.3 points)

   b) Given that C is held constant at zero or one and X and Y are initially at the values you proposed for part a, what happens to the outputs if there is a pulse of the opposite value on the X input. (0.4 points)

3. Background: Look at the code for the Hawk monitor. As written, when a trap occurs, for example, a bus trap, the monitor saves the registers, outputs an error message (Bus Trap.) and the value of the saved PC and Trap Memory Address, and finally, restores the registers and then does a return from trap to location 0 in memory. Setting the PC to zero halts the Hawk emulator. The result is that, when the emulator halts, all of the registers it shows hold the values they had at the tim of the instruction that caused the trap, except the PC (which is zero).

   a) It didn't really save and restore all the registers from R1 to R15. Which registers did the code actually save and restore? (0.3 points)

   b) Why didn't the monitor's trap service routine need to save the other registers? (0.5 points)

4. Background: Look at the code for the Hawk monitor and consider making changes so that the bus trap handler could raise a software exception. Obviously, the monitor would need to declare the exception, for example, following the outline at the start of chapter 13 of the notes, it could start with this:

   	COMMON  BUSTRAP, EXSIZE
   

   The monitor would install a default exception handler for a bus trap exception before launching the user program. The default handler would output the exact same error message the monitor currently outputs, and then it would halt, exactly as the current monitor does. As a consequence of this change, users could install their own handler for this (and other) trap conditions.

   There are two ways a trap handler in the monitor could transfer control to the handler:

   1. It could immediately load R2 with the EXAR field of the common, and then jump to the address in the EXHAND field of the common, or

   2. After saving the registers, it could copy the EXAR and EXHAND fields of the common into the save location for R2 and PC and then restore the registers from the save area and return from trap.

   a) Which would lead to faster trap handling? (0.3 points)

   b) Is one of these solutions incorrect in any formal sense of the word? Why? You may need to read ahead in the notes to determine this. (0.5 points)