Assignment 12, Solutions

On every assignment, write your name legibly as it appears on your University ID card! Homework is due on paper at the start of class on the day indicated (usually Friday). Exceptions will be made only by advance arrangement (excepting "acts of God"). Late work must be turned in to the TA's mailbox (ask the CS receptionist in 14 MLH for help). Never push homework under someone's door!

1. Problems from Chapter 13 of the notes:

   r) (1.0 points)

   Here is the most direct solution, simply cramming the desired value into the PSW without regard to its previous contents.

           LIW     R3,#D0000000
           CPUSET  R3,PSW
   

   A timid programmer worried that some other PSW fields might contain useful information might do this:

           CPUGET  R3,PSW
           LIW     R4,#D0000000        ; note, hex D is 1101 binary
           OR      R3,R4
           CPUSET  R3,PSW
   

   The above code assumes that the level field of the PSW is set to zero on entry to the interrupt service routine, so or-ing a value into the level field is a safe way to stuff new contents into that field.

2. Background: Consider the following subroutine. This subroutine only works correctly if it is assembled into RAM, so assume that is done.

   SL:     ; given R3 a value to be shifted left
           ; given R4 is an integer between 1 and 16 (inclusive)
           ; returns R3 shifted left R4 places
           ; wipes out R4,R5
           TRUNC   R4,4
           SL      R4,8	   ; put R4 into the shift-count field
           LIL     R5,#00A3   ; SL R3,16
           OR      R4,R5      ; compose an instruction that does SL R3,R4
           STORE   R4,SLINST  ; put it in RAM
           BR      SLINST     ; go execute it
           ALIGN   4
   SLINST: SL      R3,16      ; this instruction will be changed
           NOP
           JUMPS   R1
   

   a) Why is the ALIGN directive required and why is the NOP required? There is one explanation for both of these. (0.4 point)

   The 32-bit word with the label SLINST is not only intended to be executed, but it is also the target of a STORE instruction, and on the Hawk, STORE instructions can only manipulate aligned 32-bit words.

   b) This code used to work on a bottom-of-the-line HAWK processor. Then you bought a machine that had a simple write-through L1 cache between the CPU and memory. Would you expect it to continue working? Why? (0.4 point)

   Yes, it would continue working. The write-through cache is invisible to the CPU (except for its impact on performance).

   c) This code used to work on a bottom-of-the-line HAWK processor. Then you bought a machine that had separate I-cache and D-cache. Would you expect it to continue working? Why? (0.4 point)

   It might stop working because the STORE instruction changes the contents of the D-cache without altering the contents of the I-cache. As a result, the instruction fetch for the modified SL instruction could fetch the instruciton from I-cache, getting an old copy of the word that was preserved from before the STORE was executed. If, as luck would have it, the word at SLINST is not in the I-cache, the code might work, so long as the D-cache is a write-through cache and not some kind of high performance write-back cache that delays saving data to RAM.

3. Background Problems l) in Chapter 14 of the notes asks how the Hawk memory management unit can be used to prevent user programs from directly accessing any input-output device. The first part of the answer is obvious: Set up the MMU so that no virtual address maps to memory locations FF000000₁₆ and up. Here, we are interested in more subtle questions:

   a) How can we prevent the user program from changing the contents of the MMU? Major parts of the answer to this question depend on material presented in previous chapters of the notes. (0.4 point)

   We must prevent the program from executing CPUSET instructions that operate on the MMU, specifically involving the TMA (trap memory address) and MMUD (MMU Data) registers. Since CPUSET is illegal when the level field of the PSW is 1111, we must set the level field to 1111 when the user code is running.

   b) Suppose we wanted to be able to specifically allow user programs to access just some Hawk devices but not others, with a different subset of the devices accessible to each program. If we did not have this constraint, each device register could be arbitrarily assigned any unused 32-bit address above FF000000₁₆. How should addresses be assigned to the different device registers of each device in order to conform to this constraint. (0.4 point)

   Each device would have to have its block of device register addresses occupy one page of the address space. That is, each device would have all of its interface registers in a block of 4K bytes of the address space, running from FFXXX000 to FFXXXFFF.

   Added note: This allows for a maximum of 4K distinct devices. but note that a pixel-mapped video display with 1 million pixels could easily use 4 megabytes of video ram, using 1K pages of the address space.