Assignment 7, due Oct 15

Always write your name legibly as it appears on your University ID and on the class list!

Homework

1. Background: Here is the header for a Hawk subroutine:

           SUBTITLE "REVERSE - reverse the order of bytes in a word"
                   ; when called, it reverses the byte order of the word
   ; activation record structure
   ;RETAD  =       0
   
   REVERSE:        ; expects R3 = pointer to a word in RAM
                   ; conforms to the usual Hawk caling sequence
                   ; when called, reverses the byte order of the word
           JUMPS   R1
   

   If REVERSE is called to operate on a word containing 0123456716, the word will be changed to hold 6745230116; that is, the order of the bytes in the word will be reversed.

   The problem: Flesh out the subroutine so it works as specified. It's all a matter of extracting and stuffing the bytes. (1 point)

2. Background: The notes for Chapter 8 show that the V condition code can be computed by using an exclusive-or gate to combine the carry in to the most significant bit of the sum with the carry out of the most significant bit of the sum. There is another way to detect overflow: If you add two positive numbers and get a negative result, or if you add two negative numbers and get a positive result, there is an overflow. You never get an overflow by adding two numbers with different signs. This alternative function to compute the overflow uses just the a and b inputs and the s output of the adder for the most significant bit.

   a) Give the truth table for this alternative way to compute the V condition code. (0.5 point)

   b) Draw a schematic diagram for hardware to compute this function, using only and, or and not gates. (0.5 point)

3. Background: The bit slice of an ALU suggested in Chapter 8 of the notes is not very efficient. Note that the bit slice of an adder inside this ALU has lots of gates in it, as documented in the figure for the gate-level schematic view of an adder, which shows 7 and gates plus some or gates.

   An alternative approach to making an ALU do logic operations is to add extra inputs to the adder. Each of these extra inputs goes to one or more of the and gates in the and array of the adder. If all these extra inputs are one, the and array is fully enabled and the adder just adds. Setting each of these extra inputs to zero disables some subset of the and gates in the and array, forcing the adder to do some logic function.

   a) Which gates in the and array of the adder should you disable to make the adder perform an exclusive-or operation? Hint: add becomes exclusive-or if you make it ignore the carry in line. (0.3 point)

   b) Which gates in the and array of the adder should you disable to make the adder perform just an or operation? (0.3 point)

   c) Draw the gate-level schematic view of an addre augmented with the auxiliary inputs supporting your answers to parts a and b. (0.4 point)