SMAL32 (rev 10/08) "MP5 -- Douglas Jones" 14:18:02 Page 1 Mon Dec 14 2009 97 SUBTITLE "INSTR trap handler subroutine" 199 SUBTITLE "SLEFT and SRIGHT subroutines" SMAL32 (rev 10/08) "MP5 -- Douglas Jones" 14:18:02 Page 2 Mon Dec 14 2009 1 TITLE "MP5 -- Douglas Jones" 2 USE "hawk.macs" 3 USE "monitor.h" 4 5 ; seemingly magic constants based on the Hawk manual 6 INSTRTRAP = #20 ; trap vector address 7 SHIFTOP = #8010 ; opcode defined by this handler 8 ; Note byte order! opcode given as halfword! 9 10 ; save area used by instruction trap handler 11 COMMON INSTSAVE,SAVESIZE+SAVESTACK 12 svPC = 0 13 svR1 = 1 << 2 14 svR2 = 2 << 2 15 svR3 = 3 << 2 16 svR4 = 4 << 2 17 svR5 = 5 << 2 18 svR6 = 6 << 2 19 svR7 = 7 << 2 20 svR8 = 8 << 2 21 svR9 = 9 << 2 22 svR10 = 10 << 2 23 svR11 = 11 << 2 24 svR12 = 12 << 2 25 svR13 = 13 << 2 26 svR14 = 14 << 2 27 svR15 = 15 << 2 28 svPSW = 16 << 2 29 svMA = 17 << 2 30 SAVESIZE= 18 << 2 31 SAVESTACK= #50 32 33 ; code to install instruction trap handler 34 LCSAVE = . 35 . = INSTRTRAP ; the following code is 16 bytes 36 CPUSET R2,TSV ; 2 save R2 000020: 12 03 37 LIL R2,INSTSAVE ; 4 make savearea pointer 000022: E2 +000000 38 STORE R1,R2,svR1 ; 4 save R1 000026: F1 22 0004 39 LIL R1,HANDLER ; 4 get pointer to handler body 00002A: E1 +000000 40 JUMPS R1 ; 2 go to handler body 00002E: F0 B1 41 . = LCSAVE 42 43 ; finish save registers, call handler, restore registers and return 44 ; this code convert the trap to a normal subroutine call 45 46 HANDLER: ; R1 already saved, R2 in TSV, PC in TPC 47 CPUGET R1,TSV +000000: 11 13 48 STORE R1,R2,svR2 ; save R2 properly +000002: F1 22 0008 49 CPUGET R1,PSW +000006: 11 10 50 STORE R1,R2,svPSW ; save PSW +000008: F1 22 0040 51 CPUGET R1,TPC +00000C: 11 11 52 STORE R1,R2,svPC ; save PC +00000E: F1 22 0000 53 CPUGET R1,TMA +000012: 11 12 54 STORE R1,R2,svMA ; save TMA -- this one does not get restored +000014: F1 22 0044 55 STORE R3,R2,svR3 ; save R3 and up +000018: F3 22 000C 56 STORE R4,R2,svR4 SMAL32 (rev 10/08) "MP5 -- Douglas Jones" 14:18:02 Page 3 Mon Dec 14 2009 +00001C: F4 22 0010 57 STORE R5,R2,svR5 +000020: F5 22 0014 58 STORE R6,R2,svR6 +000024: F6 22 0018 59 STORE R7,R2,svR7 +000028: F7 22 001C 60 STORE R8,R2,svR8 +00002C: F8 22 0020 61 STORE R9,R2,svR9 +000030: F9 22 0024 62 STORE R10,R2,svR10 +000034: FA 22 0028 63 STORE R11,R2,svR11 +000038: FB 22 002C 64 STORE R12,R2,svR12 +00003C: FC 22 0030 65 STORE R13,R2,svR13 +000040: FD 22 0034 66 STORE R14,R2,svR14 +000044: FE 22 0038 67 STORE R15,R2,svR15 +000048: FF 22 003C 68 69 ; handler body is written as a normal subroutine, free to use R3-R15 70 MOVE R3,R2 ; parameter is pointer to save area +00004C: F3 F2 71 ADDI R2,R2,SAVESIZE +00004E: F2 62 0048 72 JSR R1,INSTR +000052: F1 30 004E 73 ADDI R2,R2,-SAVESIZE +000056: F2 62 FFB8 74 75 LOAD R3,R2,svR3 ; restore R3 and up +00005A: F3 52 000C 76 LOAD R4,R2,svR4 +00005E: F4 52 0010 77 LOAD R5,R2,svR5 +000062: F5 52 0014 78 LOAD R6,R2,svR6 +000066: F6 52 0018 79 LOAD R7,R2,svR7 +00006A: F7 52 001C 80 LOAD R8,R2,svR8 +00006E: F8 52 0020 81 LOAD R9,R2,svR9 +000072: F9 52 0024 82 LOAD R10,R2,svR10 +000076: FA 52 0028 83 LOAD R11,R2,svR11 +00007A: FB 52 002C 84 LOAD R12,R2,svR12 +00007E: FC 52 0030 85 LOAD R13,R2,svR13 +000082: FD 52 0034 86 LOAD R14,R2,svR14 +000086: FE 52 0038 87 LOAD R15,R2,svR15 +00008A: FF 52 003C 88 89 LOAD R1,R2,svPC ; setup for return which restores PC +00008E: F1 52 0000 90 CPUSET R1,TPC +000092: 11 01 91 LOAD R1,R2,svPSW ; restore PSW +000094: F1 52 0040 92 CPUSET R1,PSW +000098: 11 00 93 LOAD R1,R2,svR1 ; can now restore R1 +00009A: F1 52 0004 94 LOAD R2,R2,svR2 ; can now restore R2 +00009E: F2 52 0008 95 RTT ; return! +0000A2: 10 11 96 SMAL32 (rev 10/08) "MP5 -- Douglas Jones" 14:18:02 Page 4 "INSTR trap handler subrou Mon Dec 14 2009 97 SUBTITLE "INSTR trap handler subroutine" 98 ; instruction trap handler subroutine 99 ;RETAD = 0 100 ARSIZE = 4 101 102 INSTR: ; R3 points to save area 103 ; uses mundane calling sequence except free to wreck R3-R15 104 STORES R1,R2 +0000A4: F1 A2 105 106 ; diagnose cause of trap 107 LOAD R7,R3,svPC ; get saved PC to R7 +0000A6: F7 53 0000 108 LOADS R6,R7 ; get word holding instruction that trapped +0000AA: F6 D7 109 EXTH R6,R6,R7 ; get halfword that is the instruction to R6 +0000AC: 46 67 110 MOVE R4,R6 +0000AE: F4 F6 111 TRUNC R4,4 ; get dst field to R4 +0000B0: 14 F4 112 MOVE R5,R6 +0000B2: F5 F6 113 SR R5,8 +0000B4: 95 08 114 TRUNC R5,4 ; get count field to R5 +0000B6: 15 F4 115 BZR INSFXD +0000B8: 0A 01 116 LIS R5,16 ; fix so count of zero means 16 +0000BA: D5 10 117 INSFXD: 118 LIL R1,#00F0F0 +0000BC: E1 00F0F0 119 AND R6,R1 ; get pure opcode field +0000C0: 16 B1 120 121 LIL R1,SHIFTOP +0000C2: E1 008010 122 CMP R6,R1 ; compare with new shift opcode +0000C6: 20 61 123 BNE INSNOT +0000C8: 0A 17 124 CMPI R4,#1 ; check for legitimate dst register +0000CA: F0 64 FFFF 125 BLE INSNOT +0000CE: 06 14 126 127 ; it is a shift, update PC to reflect that 128 ADDSI R7,2 +0000D0: 17 C2 129 STORE R7,R3,svPC +0000D2: F7 23 0000 130 131 ; trap caused by shift instruction, R4 is dst field, R5 is count 132 BITTST R4,0 ; check direction of shift +0000D6: 90 41 133 BCS INSRGT +0000D8: 04 07 134 135 ; shift is left, R4 is dst field, R5 is count 136 ADDI R2,R2,ARSIZE +0000DA: F2 62 0004 137 JSR R1,SLEFT ; shift left( savearea = R3, dst=R4, count=R5) +0000DE: F1 30 00AE 138 ADDI R2,R2,-ARSIZE +0000E2: F2 62 FFFC 139 BR INSDONE +0000E6: 00 3A 140 141 INSRGT: ; shift is right, R4 is dst field +1, R5 is count 142 ADDSI R4,-1 ; chop off direction bit +0000E8: 14 CF 143 ADDI R2,R2,ARSIZE +0000EA: F2 62 0004 144 JSR R1,SRIGHT ; shift left( savearea = R3, dst=R4, count=R5) +0000EE: F1 30 00B6 145 ADDI R2,R2,-ARSIZE +0000F2: F2 62 FFFC 146 BR INSDONE +0000F6: 00 32 147 148 INSNOT: ; trap not caused by shift instruction 149 150 MOVE R8,R3 ; set aside trap save area pointer +0000F8: F8 F3 151 SMAL32 (rev 10/08) "MP5 -- Douglas Jones" 14:18:02 Page 5 "INSTR trap handler subrou Mon Dec 14 2009 152 ADDI R2,R2,ARSIZE +0000FA: F2 62 0004 153 ; following section based on code lifted from the hawk monitor 154 LIL R1,DSPINI +0000FE: E1 +000000 155 JSRS R1,R1 ; wipes out R3-4 +000102: F1 B1 156 LEA R3,MSGINS ; output trap name +000104: F3 70 0058 157 LIL R1,DSPST +000108: E1 +000000 158 JSRS R1,R1 ; wipes out R3-7 +00010C: F1 B1 159 LEA R3,MSGPC ; output "PC =" +00010E: F3 70 005F 160 LIL R1,DSPST +000112: E1 +000000 161 JSRS R1,R1 ; wipes out R3-7 +000116: F1 B1 162 LOAD R3,R8,svPC ; output PC value +000118: F3 58 0000 163 LIL R1,DSPHX +00011C: E1 +000000 164 JSRS R1,R1 ; wipes out R3-7 +000120: F1 B1 165 LEA R3,MSGXX ; output trailer +000122: F3 70 0067 166 LIL R1,DSPST +000126: E1 +000000 167 JSRS R1,R1 ; wipes out R3-7 +00012A: F1 B1 168 LIS R3,16 +00012C: D3 10 169 LIS R4,1 ; moveto (17,1) +00012E: D4 01 170 LIL R1,DSPAT +000130: E1 +000000 171 JSRS R1,R1 ; wipes out R3-7 +000134: F1 B1 172 LEA R3,MSGMA ; output "MA =" +000136: F3 70 0045 173 LIL R1,DSPST +00013A: E1 +000000 174 JSRS R1,R1 ; wipes out R3-7 +00013E: F1 B1 175 LOAD R3,R8,svMA ; output MA value +000140: F3 58 0044 176 LIL R1,DSPHX +000144: E1 +000000 177 JSRS R1,R1 ; wipes out R3-7 +000148: F1 B1 178 LEA R3,MSGXX ; output trailer +00014A: F3 70 003F 179 LIL R1,DSPST +00014E: E1 +000000 180 JSRS R1,R1 ; wipes out R3-7 +000152: F1 B1 181 ; end of code lifted from the hawk monitor 182 ADDI R2,R2,-ARSIZE +000154: F2 62 FFFC 183 184 STORE R0,R8,svPC ; make the return from trap force a halt. +000158: F0 28 0000 185 ; BR INSDONE 186 187 INSDONE:; ready to return from trap 188 189 LOADS R1,R2 +00015C: F1 D2 190 JUMPS R1 ; return +00015E: F0 B1 191 192 ; "0123456789ABCDEF" +000160: 49 6E 73 74 193 MSGINS: ASCII "Instruction Trap",0 72 75 63 74 69 6F 6E 20 54 72 61 70 00 +000171: 20 20 54 72 194 MSGPC: ASCII " Trap PC = #",0 61 70 20 50 43 20 3D 20 23 00 +00017F: 20 20 54 72 195 MSGMA: ASCII " Trap MA = #",0 61 70 20 4D 41 20 3D 20 23 00 +00018D: 20 20 00 196 MSGXX: ASCII " ",0 197 ALIGN 2 SMAL32 (rev 10/08) "MP5 -- Douglas Jones" 14:18:02 Page 6 "INSTR trap handler subrou Mon Dec 14 2009 198 SMAL32 (rev 10/08) "MP5 -- Douglas Jones" 14:18:02 Page 7 "SLEFT and SRIGHT subrouti Mon Dec 14 2009 199 SUBTITLE "SLEFT and SRIGHT subroutines" 200 ; shift left subroutine 201 SLEFT: ; R3 points to save area 202 ; R4 is dst field of shift instr 203 ; R5 is count field of shift instr 204 ; uses mundane calling sequence except free to wreck R3-R15 205 ADDSL R4,R3,2 ; R4 = &(savearea[R4]) -- pointer to saved register +000190: A4 32 206 LOADS R6,R4 +000192: F6 D4 207 LOAD R7,R4,4 ; R6-7 is double word operand +000194: F7 54 0004 208 209 SLFTLP: ; loop once for each bit of shift 210 SL R6,1 ; shift low half +000198: A6 01 211 ROL R7 ; shift high half +00019A: 17 77 212 ADDSI R5,-1 +00019C: 15 CF 213 BNE SLFTLP +00019E: 0A FC 214 215 STORES R6,R4 +0001A0: F6 A4 216 STORE R7,R4,4 ; put operand back in saved registers +0001A2: F7 24 0004 217 JUMPS R1 ; return +0001A6: F0 B1 218 219 ; shift right subroutine 220 SRIGHT: ; R3 points to save area 221 ; R4 is dst field of shift instr 222 ; R5 is count field of shift instr 223 ; uses mundane calling sequence except free to wreck R3-R15 224 ADDSL R4,R3,2 ; R4 = &(savearea[R4]) -- pointer to saved register +0001A8: A4 32 225 LOADS R6,R4 +0001AA: F6 D4 226 LOAD R7,R4,4 ; R6-7 is double word operand +0001AC: F7 54 0004 227 228 SRGTLP: ; loop once for each bit of shift 229 SRU R6,1 ; shift low half (unsigned!) +0001B0: 86 01 230 SR R7,1 ; shift high half +0001B2: 97 01 231 ADJUST R6,CMSB ; move bit shifted out of high half to low half +0001B4: 16 54 232 ADDSI R5,-1 +0001B6: 15 CF 233 BNE SRGTLP +0001B8: 0A FB 234 235 STORES R6,R4 +0001BA: F6 A4 236 STORE R7,R4,4 ; put operand back in saved registers +0001BC: F7 24 0004 237 JUMPS R1 ; return +0001C0: F0 B1 238 239 END no errors