Assignment 12, due Dec. 4

Always, on every assignment, please write your name legibly as it appears on your University ID and on the class list! All assignments will be due at the start of class on the day indicated (usually a Friday). The only exceptions to this rule will be by advance arrangement unless there is what insurance companies call "an act of God" - something outside your control. Homework must be turned in on paper and in class! Late work may be turned in to the teaching assistant's mailbox, but see the late work policy. Never push late work under someone's door!

Problems

1. Background: Look at the illustration entitled "A complete system" in chapter 14 of the notes. Note that the figure includes 2 L1 caches upstream of the MMU, the I cache and the D cache and one L2 cache downstream.

   Consider this program. It works if run in RAM on the Hawk emulator, but it will not work if it is run on the system described in the figure referenced above. If you try to run it in ROM, of course, it fails with a bus trap:

   SHIFT:  ; expects R3 = register to shift (from 6 to 15)
           ;         R4 = shift count (from 0 to 15)
           LOAD    R5,CODE
           OR      R5,R3
           SL      R4,8
           OR      R5,R4
           STORE   R5,INSTR
           NOP
   INSTR:  NOP			; do the shift
           NOP
           JUMPS   R1
   	ALIGN	4
   CODE:   SL	R0,16
   	NOP
   

   a) Why are so many NOP instructions needed? (0.5 points)

   b) Why doesn't this code work correctly on the system in the figure? (0.5 points)

2. Background: Consider a system designed so that cache memory circuit cards can be plugged into the memory bus in parallel with RAM cards. You plug in a 4K Acme brand brand cache card, and the system speeds up by a factor of 5.

   a) You liked this improvement, so you buy a second Acme 4K cache card and plug it into the bus. You get no improvement. Why? (0.5 points)

   b) You trade in the second Acme 4K cache card for a 4K card from Zenith, Acme's competitor, and suddenly your system is 30 percent faster. Why was it possible that a competitor's cache card would improve things when a second identical card did not? And why are two caches in parallel only likely to offer a small speedup? (0.5 points)

3. Background: Trap handlers sometimes return to the caller, for example, when a trap handler implements some aspect of a virtual machine. In other cases, the trap handler might kill the running application, for example, when the running application has accessed a nonexistant memory address.

   Programmers sometimes want a third option, the option of having the trap handler raise a software exception. In this case, the default handler for the exception would terminate the application, but the user would be free to install their own handlers.

   Consider using the exception model from Chapter 13 to implement the ILLEGAL_INSTRUCTION exception in the context of Machine Problem 5 where the trap handler sometimes returns after emulating a shift instruciton and other times raises an exception.

   a) Explain why the code fragment from Chapter 13 entitled "Raising an exception, the general case" should not be used to raise an exception from within a trap handler. (0.5 points)

   b) Explain how you would raise the exception from within the trap handler. (0.5 points)

   Notes: Do not turn in code for this, the problem asks for a explanations. Adequate explanations can be written in 3 sentences or less. We reserve the right to disregard or penalize long essays offered in answer either part.

   Finally, if you imagine that the user had the MMU turned on at the time of the trap, it may actually help you understand the answers.