1) Consider the machine from Homework 6 (the midterm), a pipelined load-store machine. Assume a simple 5-stage pipe, not a superscalar implementation, and make reasonable guesses at the following characteristics of the machine, based on the data available to you from the text or other sources for similar machines:
2) Based on your figures above, assuming no caches, what fraction of pipeline cycles would you expect to result in memory conflicts. If it matters, assume that conflicts are resolved by stalling the entire pipe until two memory cycles have been completed.
3) The assumption used above of how memory conflicts between the fetch and operand stages are handled is only one alternative. Is there any advantage to the alternative of stalling the fetch stage when there is a conflict, introducing a bubble into the pipe and letting the lower pipeline stages continue to run at full speed? Explain.
4) Based on problems 1 and 2, if separate instruction and data caches are installed, and each cache has a hit rate of, say, 90%, what effect would this have on the rate of memory conflicts? Assume the use of write-through caches, so that the cache only speeds operand fetches!