1) Consider the following features of a computer architecture. For each, comment on how that feature interferes with or does not interfere with pipelined execution of the instruction set.
1.A) A single accumulator instruction set (consider the PDP-8 as the architypical example).
1.B) DMA (direct memory access) input-output operations.
1.C) A single condition code register, as is used in almost every well known modern instruction set (I80x86, M68000, IBM 360, DEC PDP-11).
1.D) Interrupts.
2) List the conditions that might lead to the injection of bubbles into the pipeline or pipeline stalls on a pipelined implementation of the a conventional multiple general purpose register machine with a single condition code register and a five stage pipe. The pipe stages are fetch, decode, operand fetch, operate, and result save.
3) Describe how the performance of a pipelined machine could be improved by the use of a Harvard architecture (one where program and data are stored in different memory systems) instead of a Von Neumann architecture (where programs and data share one memory).
4) What is the benefit of a load-store architecture, such as that of the Data General Nova or many modern RISC processors, over a general register architecture such as the M68000, PDP-11 or VAX, with respect to pipelined execution. In the latter examples, most arithmetic instructions will be of the form "add operand to register" or "divide register by operand", where many operands are in memory. By comparison, a load-store architecture requires explicit load and store instructions to move data between registers and memory, and all arithmetic is performed on a register-to-register basis.