1) In the writeup of the minimal CISC (see the course home page), a mention is made of the fact that the microcode presented relies on a 2-phase clock. Rewrite the microcode so it relies on a one-phase clock where, as a result, conditionals depend on the prior state of the machine, not on the state after the register transfer in the current instruciton.
2) The machine design given for the minimal CISC actually does depend on the two clock phases being different. Draw the waveforms of the two clock phases (the one to clock the micro program counter and the one used to gate the clocks that go to the data half), and explain what logic delays must be accounted for in the relations between 4 clock edges (the rising and falling edges of each of two clock signals).
2) In looking at the VAX, IBM/360 and 8086 architecture, 3 excellent examples of commercially successful CISC designs given in chapter 4 of the text, there are a number of differences.
First, (part a), comment on the role of orthogonality in the design of these architectures.
Second, (part b), comment on the different approachs each of these architectures takes to coding efficiency.