Midterm Exam

Part of material for 22C:122/55:132, Spring 2003
by Douglas W. Jones
THE UNIVERSITY OF IOWA Department of Computer Science

Note: This is an open-book, open-notes exam. Please write your answers in the exam booklet supplied. Leave blank lines between your answers to different questions, and leave a margin down the side of each page. Please write your name in the form it appears on your university ID card; write your name in the blank provided on the front cover. This exam is worth 20 points and has 10 parts! Allocate about 5 minutes per part.

General Background: Several problems on this exam refer to the proposed alternative to the VAX instruction set that was distributed as a source of study questions. You should have a copy of the exam study questions handy during this exam!


  1. Background: The microinstruction format for the Xerxes 150 (a mythical computer) is as follows:
        ___ ________ ___ _________ _________ _________ _________
       | r |  rmux  | c |  next0  |  next1  |  next2  |  next3  |
    4 bits specifying which destination register or memory should receive a clock pulse during this microcycle.

    8 bits used to control any multiplexors and function selection options on the data paths to destination r.

    4 bits, specifies which 2-bit conditon should be tested in order to determine the next microinstruction.

    next0, next1, next2, next3
    12-bit fields, each gives the address of one of the potential successors of this microinstruction; the particular successor to use is determined by the 2-bit condition selected by c.

    Part a) What aspects of this microinstruction format resemble horizontal microcode? (2.0 points)

    Part b) What aspects of this microinstruction format resemble vertical microcode? (2.0 points)

    Part c) Is the microengine that executes this microcode closer to the Moore or Mealy formalism? (2.0 points)

  2. Background: A computer designer working in the early 1970's needs to design an ALU; the available MSI parts, at the time, included the SN7483 4-bit full adder, the SN74157 quadruple 2-input multiplexor with disable input, and the SN7400 quadruple nand gate. When the disable input to the multiplexor is zero, the multiplexor functions normally, when it is one, all multiplexor outputs are zero. Inputs are available in both true and complemented form. After some thought, the designer hits on the following:
                   A               B   B
                   |             __|___|__
         Bsel _____|_____________\ 0   1 /
         Bdis _____|______________\disab/  SN74157
                   |_________      \___/
                   |   _____ | ______|
                  _|__|_    _|_______|_
                 | nand |  |   adder   |____ Cin
                 |______|  |___________|
          SN7400     |___     ___|       SN7483
         Rsel _________\ 0   1 /
                     0__\disab/  SN74157

    Problem: This ALU has 4 function select inputs; therefore, it supports up to 16 possible operations; some are useless. Complete the 16-row table of operations, listing the headings on the operation select columns in the order Rsel Bdis Bsel Cin. (3.0 points).

  3. Background The alternative to the VAX proposed in the study questions had no branch, conditional branch or call instructions.

    Assume that the program counter is one of the machine's 15 general purpose registers, so that the RMA PC loads any computed branch address to the program counter.

    In addition, assume that the COND c instruction causes the next 8-bit instruction to be skipped if the condition c holds, where c is a 4-bit field specifying one of 16 tests on the condition codes.

    Part a) What sequence of instructions for this fictional machine comes close to the equivalent of a PC-relative branch with an 8-bit displacement? (Hint: it takes something like 3 or 4 primitive instructions to do this.) (2.0 points)

    Part b) If you wanted to take your sequence of instructions from part a and modify it to become a conditional branch, where would you insert the COND instruction? (2.0 points)

  4. Background The proposed alternative to the VAX has limited support for autoincrement addressing, in that the memory address register is incremented by operand load and result store operations. On the PDP-11 and VAX, autoincrement addressing was used, among other things, for PC-relative immediate and absolute addressing modes.

    Part a) Give a sequence of instructions for our proposed machine that does a post-increment autoincrement load of an operand relative to some register R. (2.0 points)

    Part b) Explain why your answer to part a will not work when R is the program counter. (2.0 points)

  5. Provocative statement: When a VAX instruction is mapped to the proposed architecture, each microinstruction on the VAX becomes one instruction in the proposed architecture.

    Question: Criticize the above provocative statement! (As written, the statement is not intended to be either true or false, but rather, to be sufficiently problematic to inspire an answer that might resemble a short essay.) (3.0 points)