An interesting Idea
In the first
Architectural Support for Programming Languages and Operating Systems
conference, one of the off-hand suggestions that was given was
interesting. The suggestion was:
The VAX instruction set, with all of its addressing modes, would
have been easier to implement and easier to use if, instead of having
a fixed set of addressing modes, it had "an addressing sub-instruction-set"
that was similar in generality to the addressing possibilities offered by
high level languages.
Thinking about this led me along the following road:
First, a VAX instruction can be thought of as being composed as follows:
- Opcode -- gives number of operands, their sizes, and the operation.
- Source operand 1
- Source operand 2
- Destination operand
Why not recode it as follows:
- Fetch source operand 1 into source1 register
- Fetch source operand 2 into source2 register
- Opcode -- Gives the operation and some size info
- Store result register in Destination operand
This implies that, in addition to the 16 general registers, we
include 3 other registers, two for source operands and one for
the result! Basic instrutions would be encoded in 1 byte each:
- ADDI, SUBI -- Integer Add, Subtract
- AND, OR -- Bitwise And, Or
- ADDF, SUBF, MULF, DIVF -- Floating Add, Sutract, Multiply, Divide
- All these take their operands from source1 and source2 and store
their results in result.
- MOV -- Move
- NOT, NEG -- Integer one's and two's complement
- NEGF -- Floating negate
- All these take their operands from source1 and store
their results in result.
- OPR r -- Operand from general register r
- 4 bits of the instruction designate a register; the contents of
that register are moved to source1; the old contents of source1
are moved to source2.
- OPCB c -- load constant operand 8-bit
- OPCW c -- load constant operand 16-bit
- OPCL c -- load constant operand 32-bit
- The constant c is sign-extended to 32 bits (if needed) and moved to
source1; the old contents of source1 are moved to source2.
The constant c comes from 1 to 4 bytes following the instruction.
- RER r -- Result to general register r
- 4 bits of the instruction designate a register; the contents of
result are moved to that register.
- MAR r -- Memory address from general register r
- 4 bits of the instruction designate a register; the contents of
that register are moved to the memory address register
- RMA r -- Memory address to general register r
- 4 bits of the instruction designate a register; the contents of
the memory address register are moved to that register
- AMA c -- Absolute memory address c
- The 32-bit constant c is loaded in the memory address register.
The constant c comes from 4 bytes following the instruction.
- OPMB -- Operand from memory 8-bits
- OPMW -- Operand from memory 16-bits
- OPML -- Operand from memory 32-bits
- The contents of the memory location addressed by the memory address
register are fetched into source1; the old contents of source 1 are
moved to source2; the memory address register is incremented by the
size of the operand.
- REMB -- Result to memory 8-bits
- REMW -- Result to memory 16-bits
- REML -- Result to memory 32-bits
- The contents result are moved to the memory location addressed by the
memory address register. The memory address register is incremented by
the size of the operand.
- MAM -- 32-bit memory address from memory
- The contents of the memory location addressed by the memory address
register are fetched into the memory address register.
- DISB c -- Add displacement to memory address, 8-bit displacement
- DISW c -- Add displacement to memory address, 16-bit displacement
- DISL c -- Add displacement to memory address, 32-bit displacement
- The constant c is sign extended to 32-bits, if necessary, and added to
the memory address register.
The constant c comes from 1 to 4 bytes following the instruction
- ADAB r -- Address register add byte displacement from register r
- ADAW r -- Address register add word displacement from register r
- ADAL r -- Address register add long displacement from register r
- 4 bits of the instruction designate a register; the contents of
that register are shifted 0, 1 or 2 places to form a byte, word or
long displacement and added to the memory address register.
Some Interesting Questions
- Think about how you'd encode the following VAX instructions on this
hypothetical machine:
MOVB rs rd -- register to register
MOVW rs (rdp) -- register to memory
MOVL rs rdp+ -- register to memory
ADDW2 rs disp(rdp) -- register to memory
In the above, rs and rd are source and destination registers,
rdp is a pointer to the destination operand, the + means autoincrement
addressing, and disp is a displacement added to the pointer.
- How efficient is our encoding compared to the VAX?
- How full is our instruction set? That is, given that an opcode is
8 bits and that some instructions have 4-bit fields reserved, how much
room is there for the kind of optimization done by the people at Xerox
on their MESA architecture.
- What new operations would you expect from such optimizations, if you
use the info from the last homework on instruction frequencies on the VAX.
- What data paths would you expect inside this CPU at the register transfer
level?