Final Study Questions

Part of the homework for 22C:122/55:132, Spring 2003
by Douglas W. Jones
THE UNIVERSITY OF IOWA Department of Computer Science

An interesting Idea

By the early 1970's, many microprogrammed machines were using fast RAM to store their microcode instead of using ROM. There were two main reasons for this: Most available ROM technologies were slower than the available RAM technology, so reading the microcode into RAM allowed faster machines. Furthermore, the first generation of LSI ROM chips were "mask programmed", so any change in the contents required manufacturing new chips -- this made microcode debugging extremely painful.

If, at startup, the machine loads its microstore from an external device, why not allow the microstore to be changed at runtime? Several vendors pursued this idea; among the best known were Burroughs, in the B 1700 and B 1800 computers, where compiler writers frequently wrote new microcode to support each new compiler.

With the universal acceptance of high-performance pipelined architectures, this approach to processor design has almost died out. (The exceptions are some floating point coprocessors where the operating system must load the microcode before any floating point instructions are used.)

However, the possibility of user customized instruction sets still intrigues programming language designers and application developers. Modern field programmable gate arrays (or FPGAs) are very fast; some use static ram cells to hold their programming, so the programming can be changed extremely quickly.

A typical FPGA consists of a number of programmable logic elements (generalized truth table elements where the programming specifies both the input and-array and the output or-array), along with a stock of registers, multiplexors, and sometimes other register-transfer level components such as adders. All of these elements, along with the inputs and outputs to the FPGA, are connected by a programmable interconnect network; each connecton in this network may be turned on or off by a single bit of the programming data for the array.

Consider the following questions:

  1. What pipeline stage or stages in a pipelined processor might be good candidates for inclusion of user programmable logic?

  2. Note that, because your base machine is a general purpose machine, this programmable logic does not permit any operations that were not already possible, all it does is allow fast compact encodings of operations that might otherwise have required long slow instruction sequences. What kinds of operations might be profitably moved to programmable logic, and what kinds of operations are unlikely to be improved by such a move.

  3. Given that some pipeline stage contains programmable logic, what interface would you suggest between this logic and user or system programs for the purpose of programming the logic.

  4. Identify any new pipeline interlock conditions that would be added by the programmable logic you have proposed in the above sections. What kinds of additions would lead to new interlock conditions? What kinds of additions do not add new interlocks?

  5. Are there alternative mechanisms for programming your programmable logic that themselves require new interlock logic? This is as opposed to data-related interlocks that might arise during use of the programmable logic.

  6. Consider the bootstrapping problem: At startup, all registers in the machine contain random values except for those where preset values are explicitly loaded by special logic. Therefore, most of the programmable logic will be programmed for a random function. If you assume this, what non-programmable functions must be supported to allow system initialization?

  7. Consider the problem of careless programmers: Assume a program tries to load the programmable logic with a new function specification, and the program makes a random error. Under what assumptions about the programmable components of the system is recovery possible? Under what assumptions are we forced to reboot the entire system?

  8. Consider the problem of context switching between multiple processes, where each process makes different use of the programmable logic. What must the system do?

The above questions are not exam questions! These are study questions intended to help motivate a number of questions on the exam. No more than half of the exam will deal with the area of these study questions. Broader issues representative of the course as a whole are guaranteed to be covered on the exam.