Final Exam, Spring 2003
Part of
22C:122, Spring 2003

Note: This is an openbook, opennotes exam. Please write your answers in the exam booklet supplied. Leave blank lines between your answers to different questions, and leave a margin down the side of each page. Please write your name in the form it appears on your university ID card; write your name in the blank provided on the front cover. This exam is worth 30 points and has 15 parts! Allocate about 8 minutes per part.
General Background: Several problems on this exam refer to the PµCPL Architecture (Pipelined MicroController with Programmable Logic), a more detailed version of the architecture proposed in the study questions distributed for this exam. Here are the relevant parts of the PµCPL specification:
___ _____ _____ _______________ 0 0 r  x  disp  store M[R[x] + disp] = R[r] ________________ 0 1 r  x  disp  load R[r] = M[R[x] + disp] ________________ 1 0 r  x  disp  immed R[r] = R[x] + disp ________________ 1 1 r  x  op  d  operate R[r] = R[x] op R[d] ________________
R[0] can mean either the program counter or the constant zero, or in contexts where neither of these makes sense, the a value of 000 in the r, x or d field can be used to select other opcodes. This will be the subject of some of the exam questions.
The interpretation of the op field of the operate instructions by the ALU stage of the pipeline is entirely programmable and will be the subject of some of the exam questions.
Consider each of the following and identify the appropriate interpretation or appropriate interpretations of R[0]. It could mean PC, it could mean the constant zero, it might be useful as both, and it might be that neither makes sense; in that case, you have found room to expand this instruction set. An example is given at the end of this list:
___ _____ _____ _______________ Part a) 0 0 r 0 0 0 disp  store M[ ? + disp] = R[r] ________________ Part b) 0 00 0 0 x  disp  store M[R[x] + disp] = ? ________________ Part c) 0 1 r 0 0 0 disp  load R[r] = M[ ? + disp] ________________ Part d) 0 10 0 0 x  disp  load ? = M[R[x] + disp] ________________ Part e) 1 0 r 0 0 0 disp  immed R[r] = ? + disp ________________ Example 1 00 0 0 x  disp  immed ? = R[x] + disp ________________
In the final example, if R[0] cannot mean the constant zero, since storing to a constant is meaningless. If R[0] means PC, however, we have a very useful instruction, an indexed branch; with a displacement of zero, this is a classic function return, and if x=0 also means the program counter, this could be a PCrelative branch.
IMMED 2,0,3 R[2] = PC + 3 LOAD PC,PC,1 PC = M[PC + 1] CONST F  address of F
Part a) Suppose we'd had enough "opcode space" to allow a dedicated call instruction, or more properly, a branch and link instruction that did everything a normal PµCPL jump instruction does but also saves the return address in a register. How much faster, in clock cycles, would this new call be than the call given above?
Part b) If the PµCPL pipeline is implemented the naive way, the CPU will read the constant F from memory twice. If we add some forwarding logic, we can eliminate one of these fetches. Explain why the double read, explain where the value of F can be forwarded from to eliminate the extra read, and describe, at an abstract level, the forwarding predicate that is required.
A question: What memory arbitration and cache structure would you recommend for use in the PµCPL? A toplevel description will suffice.
Part a) What must you assume about the mechanisms for accessing the programmable logic in order to bootstrap this machine?
Part b) What must you assume about the mechanisms for accessing the programmable logic in order to allow interrupt handling on this machine?
Part a) How many bits would you expect to be needed control a general purpose shift network for the PµCPL? Explain your answer! That is, what might you expect each bit or group of bits control?
Part b) A typical ALU has 4bits of function select, if we ignore control over carry propagation. Given this, how many bits would you want in the op field for complete control over the ALU and shifters?
Part c) Here is a proposal for the programmable logic in our ALU: In addition to a carry propagation control register, we allow each bit of control input to the ALU and shifters to be computed as the programmed and of any of the bits in the op field, or their inverses. How many bits does it take to program each bit of control input, and how many control registers would you use to hold these bits?
Part d) Combining your answers to parts b and c, how many control registers are required to control the programmable ALU stage of our pipeline?
Problem: The interlock required and the need for interlocks depends on which stage does the work. For each of the possibilities listed above, is interlock logic required? In each case, must an operate instruction be blocked to await the loading of a logic control register, or must the loading be blocked to await completion of an operate instruction?