Assignment 12, due May 2
Always, on every assignment, please write your name legibly as it appears on your University ID and on the class list!
CPU CPU CPU CPU | | | | ======== ======== crossbars | | | | | \ / | | \/ | | /\ | | / \ | | | | | ======== ======== crossbars | | | | MEM MEM MEM MEM
Here, each crossbar switch has been drawn squashed with CPU-side connections on the top and memory connections on the bottom. We have a 4-way interleaved memory in this system! The path from any one CPU to any particular memory module is a binary tree, using the crossbar switch as a branching node in this tree.
Part A: Draw the corresponding diagram for an 8 by 8 system. In doing this, you should begin to see why it's called a butterfly switch.
Part B: In general, for n CPUs and n memory modules, how does the cost grow as a function of n. For crossbar switches, it was O(n2). Also, how does the switching delay between CPU and memory grow as a function of n. For a crossbar switch, this was O(1) (a constant independent of n).
__________ | IF |__________|------o------x-- read only memory port _|>_____|_ ___|___ | AC |__________| |I cache| | _|>_____|_ |_______| | OF |__________|------o------x-- read only memory port _|>_____|_ ___|___ | OP |__________| |O cache| | _|>_____|_ |_______| | OS |__________|-------------x-- read-write memory port | -----o--- _|_ |RAM| |___|
Problem: Under a conventional read-only cache, the only thing that caused a memory cycle to be delayed was a cache miss. Under what circumstances would a write using our modified cache cause additional delays? (There are two specific circumstances!)
Problem: Each approach has advantages and disadvantages. Consider both in the context of the I-caches of two CPU's that share access to memory through a crossbar switch, and explain these advantages and disadvantages. Your job here is most definitely not to say which is better -- that depends on experiments you can only design after you outline the potential positive and negative impacts of each design.