Assignment 11, due Apr 25

Always, on every assignment, please write your name legibly as it appears on your University ID and on the class list!

1. Background: Consider a 2-way superscalar pipelined architecture with the same 5-stage pipe we have been using through the last few weeks. Assume that there is no result forwarding, just interlock logic to guarantee that all instructions are executed as if they were executed by a single classical fetch-execute cycle.

   Assume this machine has a conditional skip instruction that can test any register and skip on any of the 6 classic skip conditions (<0 <=0 =0 !=0 >0 >=0).

   Part A: Assume the skips are executed in the operate stage of the two pipelines. Assuming no bubbles are in the pipe, where is the skipped instruction at the time the skip is executed (there are two cases you need to consider.)

   Part B: What interlock conditions must be enforced that relate specifically to skips, as opposed to operand dependencies. (Here the answer is a specific boolean predicate or predicates to prevent the instruction that is to be skipped from being executed before the instruction that skips it has a chance to do so).

   Part C: If one pipeline stage in this superscalar system stalls for any reason, what other stages stall and where are the bubbles introduced? (The answer is more complex than it was in a simple pipeline, but it could be even more complex, for example, if the machine knew how to collapse bubbles that came after stalled instructions.)

   Part D: Given everything you've learned from parts A, B and C, what stages could hold the next instruction when the skip that preceeded it reaches one of the operate stages. As in part A, there are two basic cases you must consider.

   Part E: Finally, given your answers to parts B, C and D how would the message to skip the next instruction be delivered? In more detail, where would it be delivered first, and under what circumstances would the recipient act on the message, and under what circumstances would the recipient forward that message to some other pipeline stage, what stage, and when (again, there are really two cases, but there is uniformity you can exploit to simplify the description considerably).