Assignment 10, due Apr 11

Always, on every assignment, please write your name legibly as it appears on your University ID and on the class list!

1. Background: Consider the simplified pipelined architecture given in the second half of the notes for notes for lecture 26 and summarized at the start of the notes for Lecture 27. The notes for Lecture 27 suggest that Register 15 can be used as the program counter, and in the outline for the address computation stage given in Lecture 26, there is a suggestion of how to do this in that stage. No suggestions are given for doing this in the operand store stage, and we must do so if we are to implement branches by stores to register 15.

The notes for lecture 28 do cover branch instructions, but only in terms of what must be added to earlier pipeline stages to make branches work. There is no coverage of what the operand store stage does.

A Problem: Give the details of the operand store stage that treats stores to register 15 as branch instructions. Use a level of detail comparable to the level of detail in the rest of the notes for Lecutres 26 to 28.

2. Background: At the end of the notes for Lecture 26, a list of "address modes" is given. Seven of these are listed as useful and the remainder have stars indicating that they were judged to be of no particular use.

Part A: For each starred mode, explain what it does and why this might have been deemed to be of marginal or no use.

Part B: At the start of the notes for Lecture 27, a bit of logic was suggested for the operand fetch stage that introduces a new set of addressing modes dubbed "short immediate" because they use the 4-bit register field as an immediate constant. Repeat the exercise from part A assuming that this enhancement is in place; you need not worry about modes 0001 and 0101 because they are accounted for in the notes, but which of the other starred modes have changed interpretations, and of them, what do those modes end up doing and why was the result deemed to be usless or of marginal use?

3. Background: If we adopt the convention that Register 15 is the program counter, what about the operand fetch stage? Obviously, we could check to see if the register field is 1111, and in that case, suppress the "need register value" signal (see the notes for Lecture 26), and instead, take the data from the program counter. This is simple enough that it is not worth drawing the picture, except:

Part A: If the operand fetch stage simply reaches back in the pipeline to get a copy of the current program counter, what unexpected consequences would this have for the programmer? (Consider an instruction such as ADD R15,R15,X - a memory to register add to R15, using PC relative addressing with a displacement of X for the operand; this brings out the very worst in this proposal if we use the pipeline scheme described here.)

Part B: How should we have brought the value of the program counter forward to the operand fetch stagee in order to avoid the problem we found in part A.