Always, on every assignment, please write your name legibly as it appears
on your University ID and on the class list!
Consider the following data structure, described informally:
Assume that field offsets in structures are small integers (less than 256),
and that the integer i is already loaded in some register.
With reference to the notes on the machines indicated, estimate (with
reasonable certanty), the number of machine instructions, and the number
of bytes of instruction space that it would take
to implement the statement
- Address P is a constant referring to a location somewhere in the address
space of our computer; assume the address is word-aligned, that is, that
the least significant bits are zero.
- Memory[P] holds a pointer to a structure S (so P = &S).
- Structure S has a field at offset X (this is P->X or (*P).X).
- This field is an array; element i is a 16-bit integer (P->X[i]).
- We want to assign the value 7 to this (P->X = 7).
P->X = 7
on each of the following machines:
a) the IBM System 360.
b) the DEC PDP-11.
c) the DEC VAX.
Note that the emphasis of this problem is not on the assembly language
of the machine, simple numeric answers, if they are correct, will be
granted full credit; partial credit will depend on how effectively you
document how you got your answers.
What constants can you load into the accumulator of a PDP-8 in a single
instruction cycle without any memory references and with no change in meaning
from one model to another? The notes give two examples, the microcoded
combinations of CLA IAC to load 1, and CLA CML RTL to load 2; there are many
more. Give the constants as signed decimal numbers, and for each, show
the symbolic instruction that loads it (using a notation such as that
suggested by CLA IAC if microcoding is involved).
Given the microcoded instructions (opcode group 7) of the PDP-8 and the
basic TAD, ADD and ISZ instructions of that machine, and the fact that
all of these instructions can be executed quickly, without the need for
multiple microcycles once any indirection is done, propose the data paths
(multiplexors, inverters, adders, etc) connecting the ALU of this machine
to the memory data register, the memory data bus, the accumulator and the
link bit. Clearly identify the control signals to this, with an emphasis
on allowing all of these instructions to be easily implemented.
(Note: All PDP-8 models prior to 1975 or so were based on core memory,
where all reads from core involved destructive read, and therefore, where
the full memory cycle for a read involved read followed immediately by
write; therefore, there was a memory data register to hold the value
just read so it could be re-written, and the read-modify-write cycle of
the ISZ instruction did took only a tiny amount of extra time compared
to a normal read.)