Assignment 4, due Feb 14

Part of the homework for 22C:122/55:132, Spring 2003
by Douglas W. Jones
THE UNIVERSITY OF IOWA Department of Computer Science

Always, on every assignment, please write your name legibly as it appears on your University ID and on the class list!

  1. Look at the IAS instruction set. If you were building this computer using vacuum tube technology, you might debug your system incrementally by first getting some subset of the instruction set working correctly, and then using it to test the added functions as your staff of engineers worked on getting the rest working.

    Part a) Identify the subset of the IAS instruction set you would start with.

    Part b) Identify the register transfers necessary to implement this subset. Express thenm as assignment statements with registers and memory units as source and destination operands.

    Part c) Work out the data part of the register transfer system needed to implement your subset, using a graphical notation similar to that assigned for problem 1-a in Homework 3.

  2. The Ultimate RISC architecture is horribly limited in several ways. One of them involves its lack of decent support for conditional branches testing the results of arithmetic operations. If the machine had a conditional store mechanism, we could do conditional branches in two instructions:
    		MOVE ccN,inhibit   ; inhibit next store if ccN true
    		MOVE dst,pc        ; branch (inhibited if ccN true)

    Part a) Consider assigning the address FFFE to the inhibit function. Propose a change to Figure 2 of the Ultimate RISC paper that will implement this function. You can do this with no change to the control unit.

    Hint: It takes a flipflop (call it the store-inhibit flipflop) and only a bit of logic akin to that used to allow use of PC as a destination address. Be careful to clear this at the right moment in the instruction execute cycle.

    Part b) As an alternative, consider allowing read from FFFF to read the current value in the PC, so you could do a conditional skip as:

    		MOVE ccN,acc       ; get the ccN condition code
    		MOVE pc,add        ; add the program counter to it
    		MOVE acc,pc        ; skip next instruction if ccN true
    What encoding for true and false would the condition codes require to support this model?