Assignment 2, due Jan 31
Part of
the homework for 22C:122/55:132, Spring 2003

Always, on every assignment, please write your name legibly as it appears on your University ID and on the class list!
a) Draw out the finished circuit, with no optimization, without abbreviation and without optimization.
b) Redraw the circuit, ommiting any gates with unused outputs and combining any rows that can be combined under the rules for optimization of combinational circuits for lecture 2. Draw the result using the abbreviated notation used in that section of the notes.
a) Give the state diagram for a Moore machine that implements this control unit.
b) Give a state table specification of this machine.
c) How many bits are there in the state register of this machine? How many nand gates and not gates (add them up) will be required, in the worst case, for a brute force reduction of the state table to digital logic. (optimization can improve this, so it's a worstcase bound.)
a) f = (x << 1)
b) f = (x == 1)
c) f = (x == y)
a) Give the truth table for a 1bit comparitor (the a and b inputs are 1bit binary numbers). We'll use these as the leaves of our binary tree of logic circuitry that compares nbit numbers.
b) Give the truth table for an internal node in the tree. It takes, as inputs, reports on the comparison of the most significant halves of the numbers being compared, and reports on the comparison of the least significant halves. The output reports on the full number represented by the combination of those two halves.