Exam 1

22C:122/55:132, Spring 2001

Please write your answers on the paper provided. Make sure your name is on the front page, in the same form as it appears in the official class list! Illegible and overly long answers are difficult to grade. Please leave margins around your answers!

This is an open-book, open notes exam. There is no limit placed on your use of handwritten or printed reference materials.

This exam is worth 20 points (20% of your final grade). Please budget about 2 minutes of your time per point.

An Example

Here is an example system, the heart of a low-performance 16-bit microprogrammed processor, that will be the subject several questions in the remainder of this exam.

Bus -----o------o-----------o-----o------o---/---o--------
         |      |     _-    |  ___|___   |   16  |
         |      |   CB------|-|>__B___|  |       | LA --->
         | RM--/ \    _- ___|___  |      |       | RD --->
   2  ___|___ /___\ CA--|>__A___| |      |       | SD --->
MA-/-|       |  |          _|_____|_RS--/ \    __|__
     | 4 x 16|  |         | a     b |  /___\  |  b  |
 _-_ |  RAM  |  |  BN-----|bnot  cin|--  | N<-|b<0  |
CM---|>______|  |  XE-----|xenab    |  | | Z<-|b=0  |
         |______|  AE-----|aenab  A |  | |    |_____|
                   BE-----|benab  L |  | |
                   CE-----|cenab  U |  | |
                          |_c__s____|  | |
                   CI-------|--|-------  |
                    C<------   |_________|

The following micro-control-word format will be assumed for the above system. Note that the remainder of the microinstruction format is not defined here!

    |    mem    |          alu             |  bus   |
    |___________|__________________________|________|
... |__|__|__|__|__|__|__|__|__|__|__|__|__|__|__|__| ...
    |  MA |CM|RM|BN XE AE BE CE CI|CA|CB|RS|LA RD SD|
    |     |  |  |                 |     |  |        |



    |    mem    |          alu             |  bus   |
    |___________|__________________________|________|
... |__|__|__|__|__|__|__|__|__|__|__|__|__|__|__|__| ...
    |  MA |CM|RM|BN XE AE BE CE CI|CA|CB|RS|LA RD SD|
    |     |  |  |                 |     |  |        |

       MA |use   BN XE AE BE CE|function
     -----+---  ---------------+---------
     0  0 | PC   0  0  0  0  0 | s = 0  
     0  1 | AC   0  0  0  1  0 | s = b
     1  0 | MQ   0  0  1  0  0 | s = a  
     1  1 | --   0  0  1  1  0 | s = a or b
                 0  1  0  1  0 | s = b and not a
                 0  1  1  0  0 | s = a and not b
                 0  1  1  1  0 | s = a xor b
                 0  1  1  0  1 | s = a + CI
                 0  1  1  1  1 | s = a + b + CI
                 1  0  0  1  0 | s = not b
                 1  0  1  1  0 | s = a or not b
                 1  1  1  0  0 | s = a and b
                 1  1  1  1  1 | s = (a - b - 1) + CI

Consider the system outlined in the introduction. One of the locations in the small RAM inside the processor is used as the program counter for this microprocessor. Give a sequence of micro control words that will increment the PC register. (2 points)
Consider the same system. We can left-shift any quantity by adding it to itself. Give a clearly justified estimate of the number of microcycles this system would require to do a double-precision left-shift of the AC|MQ register. (One way to justify your argument would be to list and count the register transfers required, using a high-level language notation, and confining your use of control structures to those that this architecture permits.) (2 points)
a) What features (if any) are missing from this architecture that you would need if you wanted to microcode a multiply instruction? Explain the need for any missing feature you identify. (2 points)
b) What features (if any) are missing from this architecture that you would need if you wanted to microcode a divide instruction? Explain the need for any missing feature you identify. (2 points)
Note: It is worth noting that, in computing the difference A-B using A+notB+1, carry out means A>B and no carry out means A<=B. For our purposes, a feature is a data path, function, or feedback signal to the control unit.
Background: Our low-performance microprocessor uses a bus design where both data and address lines are multiplexed on the same bus. Each memory module therefore is therefore connected to the bus by 16 data and address lines, plus 3 control lines, load address (LA), store data in addressed word (SD), and read data from addressed word (RD).
a) Give a block diagram of the structure of an 8K RAM module with 3 auxiliary inputs that the user is expected to hard-wire to set the address of the module. (3 points)
b) Show the sequence of microinstructions required to load the AC register with the contents of the memory location addressed by the A register. (3 points)
Background: There's a slight problem with the architecture given here! The register transfer logic given includes no provisions for easy instruction decoding! Suppose our instruction set has the following basic format:
```
|_______|_______|_______|_______|
|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|
|  op   | m |       addr        |
|       |   |                   |

op    -- the opcode
m     -- for memory reference opcodes, the mode
addr  -- for some address modes, the memory address
```
a) Suggest an appropriate addition to the register transfer logic given at the head of the exam to simplify the use of the different fields of the instruction word. (3 points)
b) Evaluate your suggestion by estimating the number of microinstructions it would take to decode and execute an instruction to load an immediate constant in the AC register, assuming that the previous microinstruction has set up the memory address from which the instruction will be fetched, so that your first microinstruction is the fetch itself. Justify your estimate! (One way to justify your argument would be to list and count the register transfers required, using a high-level language notation, and confining your use of control structures to those that this architecture permits.) (3 points).