Homework 10

22C:122/55:132, Spring 2001

Due Friday Apr 6, 2001, in class

Douglas W. Jones
  1. Background: A self-proclaimed computer expert asserts that, given two pipelined machines built using comparable technology and the same clock rate, the machine with more pipeline stages will usually be faster.

    A parallel argument about vector machines would hold that, given two vector machines built using comparable technology and the same clock rate, the machine with the _______ vector advantage would be faster.

    Part A: Complete the analogy between these two statements by providing the correct word (either larger or smaller) and then explain why the statements are analogous. For part a, do not assess the truth of either statement.

    Part B: Is the computer expert correct in his assertion? Explain why, or why not.

  2. Background: Moderate performance pipelined machines frequently offer full pipelining of simple operations such as load, store add and subtract, but slow pipelining of complex operations such as multiply and divide.

    Assume you are given a machine such as the pipelined example machine from lectures 25-27. This machine includes logic to stall the pipeline such as was discussed in lecture 27.

    Problem: Do a top-level design for an operate stage that is able to handle not only simple one-cycle operations such as and, or, not, add and subtract, but also complex microcoded operations such as multiply and divide. You should assume that the clock used for pipelined execution is also used to clock the microcoded execution mechanism. Your design may not require any modification of other pipeline stages!

    This problem is complex! It includes many small problems that you should clearly identify and address. Answers involving vague hand-waving will not be considered acceptable! You must convince the grader that your top-level design can be reduced to hardware!