Midterm Study Questions

Part of material for 22C:122/55:132, Spring 2004
by Douglas W. Jones
THE UNIVERSITY OF IOWA Department of Computer Science

Note: These study questions are not exam questions. There is no correct answer. No more than half of the exam will be based on this material, so you must broaden your study for the exam beyond this material.

A Hypothetical Architecture

Consider a 16-bit computer with the following resources:

	registers:  R[0 to 15], 16 bits each
		R[0] is the program counter, PC

		IR -- the 16-bit instruction register
		      IR.op = bits 15-14 of IR (the 2 MSBs)
		      IR.r1 = bits 13-10 of IR
		      IR.r2 = bits  9-6  of IR
		      IR.dd = bits  5-0  of IR
		      IR.op'= bits  5-3  of IR
		      IR.sk = bits  2-1  of IR
		      IR.st = bit    0   of IR (the LSB)

	ALU(operand1, operand2, operator)
		supports, at the very least, add, subtract,
		reverse subtract, and, or, xor.
	memory: M[0 to 65535], 64K words of 16 bits each
		some memory locations are I/O device registers
		some memory locations are RAM
		some memory locations are ROM
This computer has the following fetch execute cycle:
	    IR = M[PC]
	    PC = PC + 1
	    select case IR.op from among the following
	      0: -- operate
	 	result = ALU(R[IR.r1], R[IR.r2], IR.op')
		select case IR.sk from among the following
		  0: do nothing
		  1: if result < 0 then PC = PC + 1
		  2: if result = 0 then PC = PC + 1
		  3: if result > 0 then PC = PC + 1
		end case select
		if IR.st then R[IR.r1] = result
	      1: -- load
		R[IR.r1] = M[R[IR.r2] + IR.dd]
	      2: -- store
		M[R[IR.r2] + IR.dd] = R[IR.r1]
	      3: -- load address
		R[IR.r1] = R[IR.r2] + IR.dd
	    end case select
	end loop

So, what kinds of questions would you ask about this architecture?

For one, can you recognize how to program it? You've heard this before: The first step in evaluating a computer architecture is to evaluate whether it is, in fact, a general purpose machine. For a Von Neumann architecture, this means verifying that its memory addressing is sufficiently general to allow all possible data and control structures to be exploited.

Also, of course, you must be able to construct a variety of control structures. How do you do a branch on this machine? What range of relative branches does it support? Can you figure out how to call a subroutine (hint, it takes 2 instructions where most machines would take only one).

Can yo do a register-to-register move? How do you load constants? Would a programmer be likely to load zero in some register and leave it there for some reason?

A second broad class of questions revolves around implementation of this instruction set.

Work out the register-transfer logic for this machine, assuming a one-port register file. This will involve using temporary registers to hold operands at various points, and many instructions will require multiple cycles to read and write various registers during each instruction cycle. So, this will be a low performance machine. Therefore, consider writing vertical microcode to control it. Suggest an appropriate microcode format for this machine.

Work out the register-transfer logic for this machine, assuming a register file that allows 3 simultaneous accesses, with 2 read-ports and one write-port, and with edge-triggered behavior. This allows lots of parallelism! Suggest an appropriate structure for the control unit to exploit this parallelism.