# Midterm Study Questions

Note: These study questions are not exam questions. There is no correct answer. No more than half of the exam will be based on this material, so you must broaden your study for the exam beyond this material.

## A Hypothetical Architecture

Consider a 16-bit computer with the following resources:

```	registers:  R[0 to 15], 16 bits each
R[0] is the program counter, PC

IR -- the 16-bit instruction register
IR.op = bits 15-14 of IR (the 2 MSBs)
IR.r1 = bits 13-10 of IR
IR.r2 = bits  9-6  of IR
IR.dd = bits  5-0  of IR
IR.op'= bits  5-3  of IR
IR.sk = bits  2-1  of IR
IR.st = bit    0   of IR (the LSB)

ALU(operand1, operand2, operator)
supports, at the very least, add, subtract,
reverse subtract, and, or, xor.

memory: M[0 to 65535], 64K words of 16 bits each
some memory locations are I/O device registers
some memory locations are RAM
some memory locations are ROM
```
This computer has the following fetch execute cycle:
```	loop
IR = M[PC]
PC = PC + 1
select case IR.op from among the following
0: -- operate
result = ALU(R[IR.r1], R[IR.r2], IR.op')
select case IR.sk from among the following
0: do nothing
1: if result < 0 then PC = PC + 1
2: if result = 0 then PC = PC + 1
3: if result > 0 then PC = PC + 1
end case select
if IR.st then R[IR.r1] = result
R[IR.r1] = M[R[IR.r2] + IR.dd]
2: -- store
M[R[IR.r2] + IR.dd] = R[IR.r1]
R[IR.r1] = R[IR.r2] + IR.dd
end case select
end loop
```