1.
a) IF stage and ALU/MEM stage.

b) All the stages before the stage that causes trap
       will be invalid.
   All the stages after that stage 
       will be allowed to finish.
   The new instruction will be injected in
       that stage.
   The pc in that stage will be saved.

c)It is precise.


2.
a)
10% *(1/2+1/4+1/8)= 8.75*e7 (memory cycles /sec).
80/7 nanoseconds/memory cycles.

b)
10%*1/2*10%*(1/4+1/8)=3/1600


3.
write_through_cached_ram( addr, data, op )
	{
	    
	    int row;

	    -- search the cache
            row = addr & 0x00FF;  	    
	    -- search the cache
	    if op == read {
		if (cache[row].tag != addr)
		    cache[row].data = classic_ram( addr, data, op );
		return cache[row].data;
	    } else { -- op == write
		classic_ram( addr, data, op );
		cache[row].data = data;
		cache[row].tag = addr;
	    }
	}