1. a) ... ... ______________ |___IR_________| | | ------------------------o | | | | ___|__ | |skip | | |______| nop | | _________ | | | | ___ | ___ | | | o| \ | | | __|___|____ | | )--o-|D Q|-\_1___0___/ |--|___/ | | | clock-----------------|> | | |___| | | | ... ... b) If there is a bubble after the skip instruction, the bubble will be skipped and the next invalid instruction that should be skipped will not be skipped. IF the flipflop use the interclock as its clock, stall will not cause any problem. Because flipflop stores the skip information, and when the next instruction comes, it will be skipped. c) IF the branch instruction is followed by a skip instuction and skip is after IF stage, then the skip information will be stored in the flipflop and it will cause the first instruction branched to being skipped. 2. -- ALUa ALUb memory control - - Rt = 0; - - - Ri = 1; - LP: - - Ra = a[Ri]; - - - Rb = b[Ri]; - - = Ra * Rb; - - - Ra = Rt + Ra; - - - Rt = --------- _ - - - Ri = Ri + 1; - - - Ra = Ri + -10; - - - - if Ra < 0, goto LP; Optimized: -- ALUa ALUb memory control - - Rt = 0; - - - Ri = 1; - - - Rj = 10; - - - R1 = 1; - - Rj = Rj - R1; Ra = a[Ri]; - - Ri = Ri + R1; Rb = b[Ri]; - LP:Rt = Ra * Rb; Rj = Rj - R1; Ra = a[Ri]; - Rc = Rt + Rc; Ri = Ri + R1; Rb = b[Ri]; if Rj > 0, goto LP; Rt = Ra * Rb; - - - Rc = Rt + Rc; - - - Rt = --- - - - 3. Active record: _________ |_________|FIB2 = 4 |_________|FIB1 = 3 |_________|VALUE = 2 |_________|CP = 1 |_________|DL = 0 AR: R1 NR: R2 RA: R3 I : R4 --store the parameter i ---calling sequence load-address NR AR 5 store I NR VALUE ---save registers to *AR load RA R0 2 load R0 R0 0 FIB ---restore registers from *AR ------------------------ ---receiving sequence FIB: store RA AR CP store AR NR DL load-address AR NR 0 ------------------------ ---return sequence load AR AR DL load RA AR CP load-address R0 RA 0